公开(公告)号：US20200043536A1

公开(公告)日：2020-02-06

申请号：US15735625

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: An embodiment includes an apparatus comprising: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, comprising a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

公开(公告)号：US10418415B2

公开(公告)日：2019-09-17

申请号：US16069165

申请日：2016-03-28

Applicant: Intel Corporation

Inventor： Christopher J. Wiegand ,  Oleg Golonzka ,  MD Tofizur Rahman ,  Brian S. Doyle ,  Mark L. Doczy ,  Kevin P. O'Brien ,  Kaan Oguz ,  Tahir Ghani ,  Satyarth Suri

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01F41/32 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027 ,  H01L21/311 ,  H01L21/321 ,  H01L21/3213

Abstract: Approaches for an interconnect cladding process for integrating magnetic random access memory (MRAM) devices, and the resulting structures, are described. In an example, a memory structure includes an interconnect disposed in a trench of a dielectric layer above a substrate, the interconnect including a diffusion barrier layer disposed at a bottom of and along sidewalls of the trench to an uppermost surface of the dielectric layer, a conductive fill layer disposed on the diffusion barrier layer and recessed below the uppermost surface of the dielectric layer and an uppermost surface of the diffusion barrier layer, and a conductive capping layer disposed on the conductive fill layer and between sidewall portions of the diffusion barrier layer. A memory element is disposed on the conductive capping layer of the interconnect.

公开(公告)号：US20190280047A1

公开(公告)日：2019-09-12

申请号：US16320306

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Tejaswik K. Indukuri ,  Ravi Pillarisetty ,  Elijah V. Karpov ,  Satyarth Suri

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/11507

Abstract: Substrates, assemblies, and techniques for enabling a dual pedestal for resistive random access memory are disclosed herein. For example, in some embodiments, a device may include a substrate, wherein the substrate includes a fill metal, a first pedestal on the substrate, wherein the first pedestal is over the fill metal, and a second pedestal over the first pedestal, where the second pedestal is a bottom electrode for a memory cell. In an example, the first pedestal extends at least a length of the fill metal and the second pedestal extends less than a length of the first pedestal. In addition, the device can include a memory cell over the second pedestal.

公开(公告)号：US10395707B2

公开(公告)日：2019-08-27

申请号：US15503359

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Mark L. Doczy ,  Kaan Oguz ,  Brian S. Doyle ,  Charles C. Kuo ,  Robert S. Chau ,  Satyarth Suri

IPC: H01L43/10 ,  H01L43/12 ,  G11C11/16 ,  H01F10/32 ,  H01L27/22

Abstract: A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20190189913A1

公开(公告)日：2019-06-20

申请号：US16329169

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Kaan Oguz ,  Satyarth Suri ,  Kevin O'Brien ,  Mark Doczy ,  Charles Kuo

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/16 ,  G11C11/161 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.

公开(公告)号：US10707409B2

公开(公告)日：2020-07-07

申请号：US15882546

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

公开(公告)号：US20180166625A1

公开(公告)日：2018-06-14

申请号：US15882546

申请日：2018-01-29

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.

公开(公告)号：US09496486B2

公开(公告)日：2016-11-15

申请号：US14812655

申请日：2015-07-29

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

公开(公告)号：US09224794B2

公开(公告)日：2015-12-29

申请号：US13868273

申请日：2013-04-23

Applicant: Intel Corporation

Inventor： Steven Keating ,  Nick Lindert ,  Nadia Rahhal-Orabi ,  Brian Doyle ,  Satyarth Suri ,  Swaminathan Sivakumar ,  Lana Jong ,  Lin Sha

IPC: H01L29/92 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01G4/012 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/10852 ,  H01L28/90 ,  H01L28/91 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.

Abstract translation: 在挖掘特征（130,330,830）的垂直侧壁（132,332,832）上图案化金属（141,341,841）的方法包括将材料（350）放置在挖掘的特征中，使得部分 （435）暴露在材料上方的挖掘特征中，使用第一湿蚀刻化学法将金属的暴露部分从垂直侧壁上蚀刻出来，并且通过使用第二湿蚀刻化学法将其去除，从挖掘的特征中去除材料 湿蚀刻化学。 所描述的方法可以用于产生适合于eDRAM设备的MIM电容器（800）。

公开(公告)号：US10580973B2

公开(公告)日：2020-03-03

申请号：US16214306

申请日：2018-12-10

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L43/02 ,  H01L43/08 ,  H01L27/22 ,  H01L43/12 ,  G11C11/16

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.