公开(公告)号：US10756198B2

公开(公告)日：2020-08-25

申请号：US15679077

申请日：2017-08-16

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Niloy Mukherjee ,  Matthew Metz ,  Jack T. Kavalieros ,  Nancy M. Zelick ,  Robert S. Chau

IPC: H01L29/40 ,  H01L29/51 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/324 ,  H01L51/52 ,  H01L31/0224 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L29/45 ,  H01L45/00 ,  H01L33/00 ,  H01B1/12 ,  H01L33/40

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US10727339B2

公开(公告)日：2020-07-28

申请号：US15119674

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Gilbert Dewey ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Ravi Pillarisetty ,  Han Wui Then ,  Niloy Mukherjee ,  Sansaptak Dasgupta

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/336 ,  H01L29/66 ,  H01L29/08 ,  H01L29/739

Abstract: Vertical semiconductor devices having selectively regrown top contacts and method of fabricating vertical semiconductor devices having selectively regrown top contacts are described. For example, a semiconductor device includes a substrate having a surface. A first source/drain region is disposed on the surface of the substrate. A vertical channel region is disposed on the first source/drain region and has a first width parallel with the surface of the substrate. A second source/drain region is disposed on the vertical channel region and has a second width parallel with and substantially greater than the first width. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

公开(公告)号：US10573717B2

公开(公告)日：2020-02-25

申请号：US16198725

申请日：2018-11-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US10541305B2

公开(公告)日：2020-01-21

申请号：US16246356

申请日：2019-01-11

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Robert Chau ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Marko Radosavljevic

IPC: H01L29/15 ,  H01L27/088 ,  H01L29/775 ,  H01L29/66 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78 ,  B82Y10/00 ,  H01L29/778 ,  H01L29/20 ,  H01L23/66 ,  H01L27/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/423 ,  H01L21/02

Abstract: A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a source region electrically coupled with a first end of the channel region, and a drain region electrically coupled with a second end of the channel region. A second group III-N material on the first group III-N material serves as a charge inducing layer, and/or barrier layer on surfaces of nanowire. A gate insulator and/or gate conductor coaxially wraps completely around the nanowire within the channel region. Drain and source contacts may similarly coaxially wrap completely around the drain and source regions.

公开(公告)号：US10475706B2

公开(公告)日：2019-11-12

申请号：US15430348

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/8234

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

公开(公告)号：US20180309054A1

公开(公告)日：2018-10-25

申请号：US15755571

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Elijah V. Karpov ,  Uday Shah ,  Ravi Pillarisetty ,  Niloy Mukherjee

IPC: H01L45/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/51 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

Abstract: An embodiment includes a memory comprising: a top electrode and a bottom electrode; an oxygen exchange layer (OEL) between the top and bottom electrodes; a first oxide layer between the OEL and the bottom electrode; and a second oxide layer between the first oxide layer and the bottom electrode; wherein (a) a first plurality of oxygen vacancies are within the first oxide layer and are adjacent the OEL at a first concentration, (b) a second plurality of oxygen vacancies are within the first oxide layer and are adjacent the second oxide layer at a second concentration that is less than the first concentration, and (c) the first oxide layer includes a first oxide material different from a second oxide material included in the second oxide layer. Other embodiments are described herein.

公开(公告)号：US10096709B2

公开(公告)日：2018-10-09

申请号：US15119345

申请日：2014-03-28

Applicant: Intel Corporation

Inventor： Van H. Le ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Matthew V. Metz ,  Niloy Mukherjee ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/267 ,  H01L29/08 ,  H01L29/165 ,  H01L29/739

Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.

公开(公告)号：US09876014B2

公开(公告)日：2018-01-23

申请号：US15270795

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Been-Yih Jin ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Roza Kotlyar ,  Willy Rachmady ,  Niloy Mukherjee ,  Gilbert Dewey ,  Robert S. Chau

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L21/283 ,  H01L29/15 ,  H01L29/775 ,  H01L29/165 ,  H01L29/267 ,  H01L29/778 ,  H01L29/51

CPC classification number: H01L27/092 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/155 ,  H01L29/165 ,  H01L29/267 ,  H01L29/517 ,  H01L29/66431 ,  H01L29/66522 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7782

Abstract: A quantum well transistor has a germanium quantum well channel region. A silicon-containing etch stop layer provides easy placement of a gate dielectric close to the channel. A group III-V barrier layer adds strain to the channel. Graded silicon germanium layers above and below the channel region improve performance. Multiple gate dielectric materials allow use of a high-k value gate dielectric.

公开(公告)号：US09865684B2

公开(公告)日：2018-01-09

申请号：US14707292

申请日：2015-05-08

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/04 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L21/308

CPC classification number: H01L29/1033 ,  H01L21/3086 ,  H01L29/04 ,  H01L29/0665 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.

公开(公告)号：US09818870B2

公开(公告)日：2017-11-14

申请号：US14914847

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Van H. Le ,  Ravi Pillarisetty ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack T. Kavalieros ,  Robert S. Chau ,  Benjamin Chu-Kung ,  Roza Kotlyar

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/10 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/51 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7842 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/512 ,  H01L29/66439 ,  H01L29/66568 ,  H01L29/775 ,  H01L29/778 ,  H01L29/78696

Abstract: An apparatus including a heterostructure disposed on a substrate and defining a channel region, the heterostructure including a first material having a first band gap less than a band gap of a material of the substrate and a second material having a second band gap that is greater than the first band gap; and a gate stack on the channel region, wherein the second material is disposed between the first material and the gate stack. A method including forming a first material having a first band gap on a substrate; forming a second material having a second band gap greater than the first band gap on the first material; and forming a gate stack on the second material.