公开(公告)号：US20210280463A1

公开(公告)日：2021-09-09

申请号：US16809905

申请日：2020-03-05

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Brandon C. Marin ,  Leonel Arana ,  Matthew Tingey ,  Oscar Ojeda ,  Hsin-Wei Wang ,  Suddhasattwa Nad ,  Srinivas Pietambaram ,  Gang Duan

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A conductive route for an integrated circuit assembly may be formed using a sequence of etching and passivation steps through layers of conductive material, wherein the resulting structure may include a first route portion having a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, an etch stop structure on the first route portion, a second route portion on the etch stop layer, wherein the second route portion has a first surface, a second surface, and at least one side surface extending between the first surface and the second surface, and a passivating layer abutting the at least one side surface of the second route portion.

公开(公告)号：US10798817B2

公开(公告)日：2020-10-06

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/538 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K3/06 ,  H05K3/30 ,  H05K3/40 ,  H05K3/28

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.

公开(公告)号：US20240101413A1

公开(公告)日：2024-03-28

申请号：US17954522

申请日：2022-09-28

Applicant: Intel Corporation

Inventor： Jeremy D. Ecton ,  Brandon C. Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Oladeji Fadayomi ,  Oscar Ojeda

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/0006 ,  B81C1/00095 ,  B81C1/00523 ,  B81C1/00611 ,  B81B2207/07 ,  B81C2201/0123

Abstract: Disclosed herein are microelectronics package architectures having self-aligned air gaps and methods of manufacturing the same. The microelectronics packages may include first and second substrates, first and second traces, and a photosensitive material. The first trace may be attached to the first substrate and comprise a first sidewall. The second trace may be attached to the first substrate and comprise a second sidewall. The second traced may be spaced a distance from the first trace with the second sidewall facing the first sidewall. First and second portions of the photosensitive material may be attached to the first and second sidewalls, respectively. The second substrate may be attached to the first and second traces. The first and second substrates and the first and second traces may form the air gap in between the first and second traces.

公开(公告)号：US11116084B2

公开(公告)日：2021-09-07

申请号：US16634804

申请日：2017-09-27

Applicant: INTEL CORPORATION

Inventor： Jeremy Ecton ,  Nicholas Haehn ,  Oscar Ojeda ,  Arnab Roy ,  Timothy White ,  Suddhasattwa Nad ,  Hsin-Wei Wang

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/498 ,  H05K3/18 ,  H05K5/00

Abstract: Techniques and mechanisms for providing anisotropic etching of a metallization layer of a substrate. In an embodiment, the metallization layer includes grains of a conductor, wherein a first average grain size and a second average grain size correspond, respectively, to a first sub-layer and a second sub-layer of the metallization layer. The first sub-layer and the second sub-layer each span at least 5% of a thickness of the metallization layer. A difference between the first average grain size and the second average grain size is at least 10% of the first average grain size. In another embodiment, a first condition of metallization processing contributes to grains of the first sub-layer being relatively large, wherein an alternative condition of metallization processing contributes to grains of the second sub-layer being relatively small. A grain size gradient across a thickness of the metallization layer facilitates etching processes being anisotropic.

公开(公告)号：US10515824B2

公开(公告)日：2019-12-24

申请号：US15868942

申请日：2018-01-11

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Leonel Arana ,  Nicholas S. Haehn ,  Hsin-Wei Wang ,  Oscar Ojeda ,  Arnab Roy

IPC: H01L21/321 ,  H01L21/3213 ,  C23F1/14 ,  H01L21/48

Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.

公开(公告)号：US20190304912A1

公开(公告)日：2019-10-03

申请号：US15937645

申请日：2018-03-27

Applicant: INTEL CORPORATION

Inventor： Jeremy D. Ecton ,  Hiroki Tanaka ,  Oscar Ojeda ,  Arnab Roy ,  Vahidreza Parichehreh ,  Leonel R. Arana ,  Chung Kwang Tan ,  Robert A. May

IPC: H01L23/538 ,  H01L21/48

Abstract: Embodiments include a package structure with one or more layers of dielectric material, where an interconnect bridge substrate is embedded within the dielectric material. One or more via structures are on a first surface of the embedded substrate, where individual ones of the via structures comprise a conductive material and have a tapered profile. The conductive material is also on a sidewall of the embedded substrate.

公开(公告)号：US20190304890A1

公开(公告)日：2019-10-03

申请号：US15942864

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Hiroki Tanaka ,  Kristof Kuwawi Darmawikarta ,  Oscar Ojeda ,  Arnab Roy ,  Nicholas Haehn

IPC: H01L23/498 ,  H01L23/14 ,  H01L23/00 ,  H01L21/48 ,  H01L21/027 ,  G03F7/039 ,  G03F7/038 ,  G03F7/20 ,  G03F7/26

Abstract: Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.

公开(公告)号：US20180376585A1

公开(公告)日：2018-12-27

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalea ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/06 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/0283 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H05K1/115 ,  H05K1/189 ,  H05K3/064 ,  H05K3/284 ,  H05K3/303 ,  H05K3/4053 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/043

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.