公开(公告)号：US20220093535A1

公开(公告)日：2022-03-24

申请号：US17029866

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Roy Dittler ,  Darko Grujicic ,  Chandrasekharan Nair ,  Rengarajan Shanmugam

IPC: H01L23/64 ,  H01F27/32 ,  H01F27/28 ,  H01F27/24

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US12159844B2

公开(公告)日：2024-12-03

申请号：US17029866

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Roy Dittler ,  Darko Grujicic ,  Chandrasekharan Nair ,  Rengarajan Shanmugam

IPC: H01L29/00 ,  H01F27/24 ,  H01F27/28 ,  H01F27/32 ,  H01L23/64

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US11291122B2

公开(公告)日：2022-03-29

申请号：US16637545

申请日：2017-09-22

Applicant: Intel Corporation

Inventor： Darko Grujicic ,  Rengarajan Shanmugam ,  Sandeep Gaan ,  Adrian Bayraktaroglu ,  Roy Dittler ,  Ke Liu ,  Suddhasattwa Nad ,  Marcel A. Wall ,  Rahul N. Manepalli ,  Ravindra V. Tanikella

IPC: C23C18/38 ,  H05K3/38 ,  C23C18/16 ,  C23C18/18 ,  H01L21/48 ,  H05K3/42 ,  H05K3/46 ,  H05K1/11 ,  H01L23/14

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

公开(公告)号：US11791228B2

公开(公告)日：2023-10-17

申请号：US16380486

申请日：2019-04-10

Applicant: Intel Corporation

Inventor： Brandon C. Marin ,  Kristof Darmawikarta ,  Roy Dittler ,  Jeremy Ecton ,  Darko Grujicic

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/488

CPC classification number: H01L23/3114 ,  H01L23/3128 ,  H01L23/488

Abstract: Embodiments disclosed herein include electronic packages with a ground plate embedded in the solder resist that extends over signal traces. In an embodiment, the electronic package comprises a substrate layer, a trace over the substrate layer, and a first pad over the substrate layer. In an embodiment, a solder resist is disposed over the trace and the first pad. In an embodiment a trench is formed into the solder resist, and the trench extends over the trace. In an embodiment, a conductive plate is disposed in the trench, and is electrically coupled to the first pad by a via that extends from a bottom surface of the trench through the solder resist.

公开(公告)号：US20180376585A1

公开(公告)日：2018-12-27

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalea ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/06 ,  H05K1/18 ,  H05K1/11 ,  H05K3/40 ,  H05K3/46 ,  H05K3/30

CPC classification number: H05K1/0283 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H05K1/115 ,  H05K1/189 ,  H05K3/064 ,  H05K3/284 ,  H05K3/303 ,  H05K3/4053 ,  H05K3/4682 ,  H05K2201/0133 ,  H05K2201/09263 ,  H05K2203/043

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.

公开(公告)号：US11501967B2

公开(公告)日：2022-11-15

申请号：US16269357

申请日：2019-02-06

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Roy Dittler ,  Darko Grujicic ,  Marcel Wall ,  Rahul Manepalli

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

公开(公告)号：US10798817B2

公开(公告)日：2020-10-06

申请号：US15780327

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Javier Soto Gonzalez ,  Meizi Jiao ,  Shruti R. Jaywant ,  Oscar Ojeda ,  Sashi S. Kandanur ,  Srinivas Venkata Ramanuja Pietambaram ,  Roy Dittler ,  Rajat Goyal ,  Dilan Seneviratne

IPC: H05K1/02 ,  H05K3/46 ,  H01L23/538 ,  H01L21/48 ,  H05K1/11 ,  H05K1/18 ,  H05K3/06 ,  H05K3/30 ,  H05K3/40 ,  H05K3/28

Abstract: Apparatus and methods are provided for flexible and stretchable circuits. In an example, a method can include forming a first flexible conductor on a substrate, the first flexible conductor including a first conductive trace surrounded on three sides by a first dielectric, and forming a second flexible conductor on top of the first flexible conductor, the first flexible conductor located between the second flexible conductor and the substrate, the second flexible conductor including a second conductive trace surrounded by a second dielectric.