公开(公告)号：US20250112165A1

公开(公告)日：2025-04-03

申请号：US18478250

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Brandon Marin ,  Hiroki Tanaka ,  Robert May ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Numair Ahmed ,  Jeremy Ecton ,  Benjamin Taylor Duong ,  Bai Nie ,  Haobo Chen ,  Xiao Liu ,  Bohan Shan ,  Shruti Sharma ,  Mollie Stewart

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00

Abstract: Anisotropic conductive connections for interconnect bridges and related methods are disclosed herein. An example a package substrate for an integrated circuit package, the package substrate comprising a first pad disposed at a first end of an interconnect within the package substrate, the first pad disposed in a cavity in the package substrate, an interconnect bridge disposed in the cavity, the interconnect bridge including a second pad, and a third pad, and a layer disposed between the first pad and the second pad, the layer having a first conductivity between the first pad and the second pad, the layer having a second conductivity between the second pad and the third pad, the first conductivity greater than the second conductivity.

公开(公告)号：US20250112138A1

公开(公告)日：2025-04-03

申请号：US18374592

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Gang Duan ,  Sameer Paital ,  Zhixin Xie ,  Rahul Manepalli ,  Jieying Kong

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15

Abstract: Microelectronic integrated circuit package structures include an apparatus having a substrate comprising a layer of glass, the substrate comprising one or more through glass vias (TGVs) extending through the layer of glass. Individual TGVs comprise a TGV sidewall, an organic dielectric layer on the TGV sidewall and a conductive layer on the organic dielectric layer.

公开(公告)号：US20250112100A1

公开(公告)日：2025-04-03

申请号：US18375209

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Robert May ,  Hiroki Tanaka ,  Tarek Ibrahim ,  Lilia May ,  Jason Gamba ,  Benjamin Duong ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad ,  Jeremy Ecton

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

Abstract: An IC die package includes first and second IC die on a first surface of a glass layer, a bridge under the first and second IC die within an opening in the glass layer, and first and second package conductive features on a second surface of the glass layer opposite the first side. First interconnects comprising solder couple the bridge with the first and second IC die. Second interconnects excluding solder couple the first and second IC die with vias extending through the glass layer to the first package conductive features. Third interconnects excluding solder couple the bridge with the second package conductive features. The bridge couples the first and second IC die with each other, and the first and second IC die with the second package conductive features. A pitch of conductive features in the first interconnects is less than a pitch of conductive features in the second interconnects.

公开(公告)号：US20250006616A1

公开(公告)日：2025-01-02

申请号：US18216521

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Jason Steill ,  Srinivas Pietambaram ,  Marcel Wall

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: IC die package with hybrid metallization surfaces. Routing metallization features have lower surface roughness for reduced high-frequency signal transmission losses while IC die attach metallization features have higher surface roughness for greater adhesion. Routing and die attach features may be formed within a same package metallization level, for example with a plating process. An insulator material may be formed over the surface of the metallization features, for example with a dry film lamination process. Optionally, an interface material may be deposited upon at least the routing features to enhance adhesion of the insulator material to metallization surfaces of low roughness. An opening in the insulator material may be formed to expose a surface of a die attach feature. The exposed surface may be selectively roughened, and an IC die attached to the roughened surface.

公开(公告)号：US20240222139A1

公开(公告)日：2024-07-04

申请号：US18090879

申请日：2022-12-29

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Gang Duan ,  Jeremy Ecton ,  Srinivas Pietambaram

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L21/4842 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16258

Abstract: Microelectronic integrated circuit package structures include a solder joint structure having a first portion on a die and a second portion on a substrate. The first portion comprises a first metal. An inner portion of the second portion comprises a second metal, and an outer portion of the second portion comprises an intermetallic compound (IMC) of the first and second metals.

公开(公告)号：US20240222035A1

公开(公告)日：2024-07-04

申请号：US18090305

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Kristof Darmawikarta ,  Benjamin Duong ,  Gang Duan ,  Srinivas Pietambaram ,  Brandon Marin ,  Jeremy Ecton ,  Jason Steill ,  Thomas Sounart ,  Darko Grujicic

IPC: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/48 ,  H01L23/498 ,  H01L25/16

CPC classification number: H01G4/33 ,  H01G4/012 ,  H01G4/252 ,  H01L21/486 ,  H01L23/49827 ,  H01L25/165 ,  H01L23/3675

Abstract: Apparatuses, capacitor structures, assemblies, and techniques related to package substrate embedded capacitors are described. A capacitor architecture includes a multi-layer capacitor structure at least partially within an opening extending through an insulative material layer of a package substrate or on a package substrate. The multi-layer capacitor structure includes at least two capacitor dielectric layers interleaved with a plurality of conductive layers such that the capacitor dielectric layers are at least partially within the opening and one of the conductive layers are on a sidewall of the opening.

公开(公告)号：US20240219644A1

公开(公告)日：2024-07-04

申请号：US18090260

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Benjamin Duong ,  Hiroki Tanaka ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram ,  Hari Mahalingam

IPC: G02B6/35 ,  G02B6/42 ,  H01L23/498

CPC classification number: G02B6/35 ,  G02B6/4274 ,  H01L23/49816

Abstract: An integrated circuit (IC) module includes a photonic IC, an electrical IC, and a switchable waveguide device that, using a signal from the electrical IC, controls optical signals to or from the photonic IC. The switchable waveguide device may be formed by coupling metallization structures on both sides of, and either level with or below, a nonlinear optical material. The metallization structures may be in the photonic or electrical IC. The nonlinear optical material may be above the electrical IC in the photonic IC or on a glass substrate. The photonic and electrical ICs may be hybrid bonded or soldered together. The IC module may be coupled to a system substrate.

公开(公告)号：US20240194657A1

公开(公告)日：2024-06-13

申请号：US18080152

申请日：2022-12-13

Applicant: Intel Corporation

Inventor： Suddhasattwa Nad ,  Brandon Marin ,  Jeremy Ecton ,  Gang Duan ,  Srinivas Pietambaram

IPC: H01L25/16 ,  G02B6/42 ,  H01L21/56 ,  H01L23/00 ,  H01L23/433

CPC classification number: H01L25/167 ,  G02B6/4239 ,  G02B6/4245 ,  G02B6/4257 ,  G02B6/4269 ,  H01L21/565 ,  H01L23/4334 ,  H01L24/08 ,  H01L24/80 ,  G02B6/426 ,  H01L24/16 ,  H01L2224/08121 ,  H01L2224/08148 ,  H01L2224/16225 ,  H01L2224/80895 ,  H01L2924/1431 ,  H01L2924/182

Abstract: Apparatuses, systems, assemblies, and techniques related to integrating photonics integrated circuit devices and electronic integrated circuit devices into an assembly or module are described. An integrated module includes a photonics integrated circuit device within an opening of a glass core substrate and an electronic integrated circuit device direct bonded to the photonics integrated circuit device. An optical waveguide is within or on the glass core substrate and has a terminal end edge coupled to the photonics integrated circuit device within the opening.

公开(公告)号：US20240113075A1

公开(公告)日：2024-04-04

申请号：US17956363

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Marin ,  Srinivas Pietambaram ,  Gang Duan ,  Suddhasattwa Nad

IPC: H01L25/065 ,  H01L21/52 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L21/52 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389

Abstract: Multi-die packages including a glass substrate within a space between adjacent IC dies. Two or more IC die may be placed within recesses formed in a glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. Organic package dielectric material may then be built up on both sides of the IC dies and glass substrate. Metallization features formed within package dielectric material built up on a first side of the IC die may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects. Metallization features formed within package dielectric material built up on a second side of the first and second IC dies may electrically interconnect the first IC die to the second IC die.

公开(公告)号：US20240112971A1

公开(公告)日：2024-04-04

申请号：US17957359

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Yiqun Bai ,  Dingying Xu ,  Srinivas Pietambaram ,  Hongxia Feng ,  Gang Duan ,  Xiaoying Guo ,  Ziyin Lin ,  Bai Nie ,  Haobo Chen ,  Kyle Arrington ,  Bohan Shan

IPC: H01L23/15 ,  H01L21/02 ,  H01L23/495

CPC classification number: H01L23/15 ,  H01L21/02354 ,  H01L23/49506

Abstract: An integrated circuit (IC) device comprises a substrate comprising a glass core. The glass core comprises a first surface and a second surface opposite the first surface, and a first sidewall between the first surface and the second surface. The glass core may include a conductor within a through-glass via extending from the first surface to the second surface and a build-up layer. The glass cord comprises a plurality of first areas of the glass core and a plurality of laser-treated areas on the first sidewall. A first one of the plurality of laser-treated areas may be spaced away from a second one of the plurality of laser-treated areas. A first area may comprise a first nanoporosity and a laser-treated area may comprise a second nanoporosity, wherein the second nanoporosity is greater than the first nanoporosity.