公开(公告)号：US11094782B1

公开(公告)日：2021-08-17

申请号：US16795081

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L29/10 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.

公开(公告)号：US20200335526A1

公开(公告)日：2020-10-22

申请号：US16390478

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

公开(公告)号：US20200227407A1

公开(公告)日：2020-07-16

申请号：US16249256

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Johann Christian Rode ,  Walid M. Hafez

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.

公开(公告)号：US20190097057A1

公开(公告)日：2019-03-28

申请号：US16203780

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H01L21/8234 ,  H03D7/16

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US12040395B2

公开(公告)日：2024-07-16

申请号：US16713648

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Ting Chang ,  Babak Fallahazad ,  Tanuj Trivedi ,  Jeong Dong Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/7816 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66704 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78696

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment a semiconductor device comprises a substrate, a source region over the substrate, a drain region over the substrate, and a semiconductor body extending from the source region to the drain region. In an embodiment, the semiconductor body has a first region with a first conductivity type and a second region with a second conductivity type. In an embodiment, the semiconductor device further comprises a gate structure over the first region of the semiconductor body, where the gate structure is closer to the source region than the drain region.

公开(公告)号：US11862703B2

公开(公告)日：2024-01-02

申请号：US17870401

申请日：2022-07-21

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Rahul Ramaswamy ,  Jeong Dong Kim ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Ting Chang ,  Nidhi Nidhi ,  Walid M. Hafez

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L29/42392 ,  H01L21/02532 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1062 ,  H01L29/165 ,  H01L29/66795

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US11688788B2

公开(公告)日：2023-06-27

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/28158 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US11658217B2

公开(公告)日：2023-05-23

申请号：US16242670

申请日：2019-01-08

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Marko Radosavljevic ,  Glenn A. Glass ,  Sansaptak Dasgupta ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/00 ,  H01L29/40 ,  H01L21/265 ,  H01L29/778 ,  H01L29/205

CPC classification number: H01L29/405 ,  H01L21/265 ,  H01L29/205 ,  H01L29/404 ,  H01L29/408 ,  H01L29/7786

Abstract: Disclosed herein are IC structures, packages, and devices assemblies that use ions or fixed charge to create field plate structures which are embedded in a dielectric material between gate and drain electrodes of a transistor. Ion- or fixed charge-based field plate structures may provide viable approaches to changing the distribution of electric field at a transistor drain to increase the breakdown voltage of a transistor without incurring the large parasitic capacitances associated with the use of metal field plates. In one aspect, an IC structure includes a transistor, a dielectric material between gate and drain electrodes of the transistor, and an ion- or fixed charge-based region within the dielectric material, between the gate and the drain electrodes. Such an ion- or fixed charge-based region realizes an ion- or fixed charge-based field plate structure. Optionally, the IC structure may include multiple ion- or fixed charge-based field plate structures.

公开(公告)号：US11626513B2

公开(公告)日：2023-04-11

申请号：US16218886

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Heli Chetanbhai Vora

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/43 ,  H01L21/285 ,  H01L29/40 ,  H01L21/02 ,  H01L29/20

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

公开(公告)号：US11581404B2

公开(公告)日：2023-02-14

申请号：US17308900

申请日：2021-05-05

Applicant: Intel Corporation

Inventor： Tanuj Trivedi ,  Jeong Dong Kim ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Rahul Ramaswamy ,  Ting Chang ,  Babak Fallahazad

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/285

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate, the first vertical arrangement of nanowires having a greater number of active nanowires than the second vertical arrangement of nanowires, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires. The integrated circuit structure also includes a first vertical arrangement of nanoribbons and a second vertical arrangement of nanoribbons above the substrate, the first vertical arrangement of nanoribbons having a greater number of active nanoribbons than the second vertical arrangement of nanoribbons, and the first and second vertical arrangements of nanoribbons having co-planar uppermost nanoribbons.