公开(公告)号：US20230197840A1

公开(公告)日：2023-06-22

申请号：US17557827

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Xiaoye Qin ,  Johann C. Rode ,  Atsunori Tanaka ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7785 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/66462

Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.

公开(公告)号：US20230132548A1

公开(公告)日：2023-05-04

申请号：US17519429

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Atsunori Tanaka ,  Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Johann C. Rode ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.

公开(公告)号：US11688788B2

公开(公告)日：2023-06-27

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L21/02 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/022 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/28158 ,  H01L29/0673 ,  H01L29/42364 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78696

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.

公开(公告)号：US11626513B2

公开(公告)日：2023-04-11

申请号：US16218886

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Heli Chetanbhai Vora

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423 ,  H01L29/43 ,  H01L21/285 ,  H01L29/40 ,  H01L21/02 ,  H01L29/20

Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.

公开(公告)号：US11881511B2

公开(公告)日：2024-01-23

申请号：US16226162

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Rahul Ramaswamy ,  Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Johann C. Rode ,  Paul B. Fischer ,  Walid M. Hafez

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/205 ,  H01L29/66 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/785

Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.

公开(公告)号：US11757027B2

公开(公告)日：2023-09-12

申请号：US16218882

申请日：2018-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann C. Rode ,  Paul Fischer ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/78 ,  H01L27/06 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/778 ,  H01L21/8236 ,  H01L21/8252 ,  H01L21/823462 ,  H01L27/0629 ,  H01L27/0883 ,  H01L29/66462 ,  H01L29/66545 ,  H01L29/78

Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.

公开(公告)号：US20200176582A1

公开(公告)日：2020-06-04

申请号：US16209039

申请日：2018-12-04

Applicant: INTEL CORPORATION

Inventor： Johann C. Rode ,  Samuel J. Beach ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Han Wui Then ,  Walid Hafez

IPC: H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-κ dielectric and a layer of high-κ dielectric on the layer of low-κ dielectric, where the layer of high-κ dielectric has a thickness at least two times the thickness of the layer of low-κ dielectric. In some cases, the layer of low-κ dielectric has a thickness no greater than 1.5 nm. The layer of high-κ dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.