公开(公告)号：US10388858B2

公开(公告)日：2019-08-20

申请号：US15503357

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin P. O'Brien ,  Brian S. Doyle ,  Kaan Oguz ,  Robert S. Chau ,  Satyarth Suri

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/08 ,  H01L43/10

Abstract: A method including forming a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a fully-crystalline sacrificial film or substrate including a crystal lattice similar to the crystal lattice of the dielectric material; and transferring the device stack from the sacrificial film to a device substrate. An apparatus including a device stack including a dielectric layer between a fixed magnetic layer and a free magnetic layer on a device substrate wherein the fixed magnetic layer and the free magnetic layer each have a crystalline lattice conforming to a crystalline lattice of the sacrificial film or substrate on which they were formed prior to transfer to the device substrate.

公开(公告)号：US10365894B2

公开(公告)日：2019-07-30

申请号：US15575334

申请日：2015-06-17

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Prashant Majhi ,  Ravi Pillarisetty ,  Elijah V. Karpov

IPC: G06F7/58 ,  H01L43/02 ,  H01L43/08

Abstract: Described is an apparatus which comprises: a magnetic tunneling junction (MTJ) device with out-of-plane magnetizations for its free and fixed magnetic layers, and configured to have a magnetization offset away from a center and closer to a switching threshold of the MTJ device; and logic for generating random numbers according to a resistive state of the MTJ device.

公开(公告)号：US10158065B2

公开(公告)日：2018-12-18

申请号：US15126682

申请日：2014-07-07

Applicant: INTEL CORPORATION

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12

Abstract: Techniques are disclosed for forming integrated circuit structures including a magnetic tunnel junction (MTJ), such as spin-transfer torque memory (STTM) devices, having magnetic contacts. The techniques include incorporating an additional magnetic layer (e.g., a layer that is similar or identical to that of the magnetic contact layer) such that the additional magnetic layer is coupled antiferromagnetically (or in a substantially antiparallel manner). The additional magnetic layer can help balance the magnetic field of the magnetic contact layer to limit parasitic fringing fields that would otherwise be caused by the magnetic contact layer. The additional magnetic layer may be antiferromagnetically coupled to the magnetic contact layer by, for example, including a nonmagnetic spacer layer between the two magnetic layers, thereby creating a synthetic antiferromagnet (SAF). The techniques can benefit, for example, magnetic contacts having magnetic directions that are substantially in-line or substantially in-plane with the layers of the MTJ stack.

公开(公告)号：US20180323367A1

公开(公告)日：2018-11-08

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L45/00

CPC classification number: H01L43/02 ,  H01L27/222 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US10832847B2

公开(公告)日：2020-11-10

申请号：US15735622

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01F10/193 ,  H01F10/32

Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

公开(公告)号：US10832749B2

公开(公告)日：2020-11-10

申请号：US15735625

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Charles C. Kuo ,  Justin S. Brockman ,  Juan G. Alzate Vinasco ,  Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  G11C11/16

Abstract: An embodiment includes an apparatus including: a substrate; a perpendicular magnetic tunnel junction (pMTJ), on the substrate, including a first fixed layer, a second fixed layer, and a free layer between the first and second fixed layers; a first dielectric layer between the first fixed layer and the free layer; and a second layer between the second fixed layer and the free layer. Other embodiments are described herein.

公开(公告)号：US10580975B2

公开(公告)日：2020-03-03

申请号：US15753468

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： Mark L. Doczy ,  Brian S. Doyle ,  Charles C. Kuo ,  Kaan Oguz ,  Kevin P. O'Brien ,  Satyarth Suri ,  Tejaswi K. Indukuri

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01F10/32 ,  H01F41/34 ,  H01L27/22

Abstract: Technologies for manufacturing spin transfer torque memory (STTM) elements are disclosed. In some embodiments, the technologies include methods for removing a re-deposited layer and/or interrupting the electrical continuity of a re-deposited layer that may form on one or more sidewalls of an STTM element during its formation. Devices and systems including such STTM elements are also described.

公开(公告)号：US10546772B2

公开(公告)日：2020-01-28

申请号：US16070172

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Richard E. Schenker ,  Hui Jae Yoo ,  Kevin L. Lin ,  Jasmeet S. Chawla ,  Stephanie A. Bojarski ,  Satyarth Suri ,  Colin T. Carver ,  Sudipto Naskar

IPC: H01L23/52 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522

Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.

公开(公告)号：US10340443B2

公开(公告)日：2019-07-02

申请号：US15735613

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Elijah V. Karpov ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau ,  Niloy Mukherjee ,  Prashant Majhi

IPC: H01L43/02 ,  H01L43/08 ,  H01L45/00 ,  H01L27/22 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.

公开(公告)号：US09882121B2

公开(公告)日：2018-01-30

申请号：US15117605

申请日：2014-03-28

Applicant: INTEL CORPORATION

Inventor： Charles C. Kuo ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  David L. Kencke ,  Satyarth Suri ,  Robert S. Chau

IPC: H01L29/82 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/02 ,  H01L43/12

Abstract: Techniques are disclosed for fabricating a self-aligned spin-transfer torque memory (STTM) device with a dot-contacted free magnetic layer. In some embodiments, the disclosed STTM device includes a first dielectric spacer covering sidewalls of an electrically conductive hardmask layer that is patterned to provide an electronic contact for the STTM's free magnetic layer. The hardmask contact can be narrower than the free magnetic layer. The first dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer. In some embodiments, the STTM further includes an optional second dielectric spacer covering sidewalls of its free magnetic layer. The second dielectric spacer can be utilized in patterning the STTM's fixed magnetic layer and may serve, at least in part, to protect the sidewalls of the free magnetic layer from redepositing of etch byproducts during such patterning, thereby preventing electrical shorting between the fixed magnetic layer and the free magnetic layer.