公开(公告)号：US20230197520A1

公开(公告)日：2023-06-22

申请号：US17557579

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Yi SHI ,  Omkar KARHADE ,  Shawna M. LIFF ,  Zhihua ZOU ,  Ryan MACKIEWICZ ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Arnab SARKAR

IPC: H01L21/822 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/822 ,  H01L21/561 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/97 ,  H01L2924/15311

Abstract: Embodiments herein relate to systems, apparatuses, or processes for attaching dummy dies to a wafer that includes a plurality of active dies, where the dummy dies are placed along or in dicing streets where the wafer is to be cut during singulation. In embodiments, the dummy dies may be attached to the wafer using a die attach film, or may be attached using hybrid bonding. Other embodiments may be described and/or claimed.

公开(公告)号：US20220254754A1

公开(公告)日：2022-08-11

申请号：US17728813

申请日：2022-04-25

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Aleksandar ALEKSOV ,  Shawna M. LIFF ,  Johanna M. SWAN ,  Patrick MORROW ,  Kimin JUN ,  Brennen MUELLER ,  Paul B. FISCHER

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.

公开(公告)号：US20210225807A1

公开(公告)日：2021-07-22

申请号：US17222815

申请日：2021-04-05

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Javier SOTO GONZALEZ ,  Shawna M. LIFF

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: An embedded silicon bridge system including tall interconnect via pillars is part of a system in package device. The tall via pillars may span a Z-height distance to a subsequent bond pad from a bond pad that is part of an organic substrate that houses the embedded silicon bridge.

公开(公告)号：US20200235082A1

公开(公告)日：2020-07-23

申请号：US16651331

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Johanna M. SWAN ,  Shawna M. LIFF

IPC: H01L25/10 ,  H01L25/00 ,  H01L23/367 ,  H01L21/48

Abstract: A device package and a method of forming the device package are described. The device package includes one or more dies disposed on a first substrate. The device packages further includes one or more interconnects vertically disposed on the first substrate, and a mold layer disposed over and around the first die, the one or more interconnects, and the first substrate. The device package has a second die disposed on a second substrate, wherein the first substrate is electrically coupled to the second substrate with the one or more interconnects, and wherein the one or more interconnects are directly disposed on at least one of a top surface of the first substrate and a bottom surface of the second substrate without an adhesive layer. The device package may include one or more interconnects having one or more different thicknesses or heights at different locations on the first substrate.

公开(公告)号：US20190297975A1

公开(公告)日：2019-10-03

申请号：US16303386

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Sasha N. OSTER ,  Feras EID ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Johanna M. SWAN ,  Baris BICEN ,  Valluri R. RAO

IPC: A41D27/28 ,  A41D13/00 ,  A41D27/24 ,  A61M35/00 ,  A61M5/145

Abstract: Embodiments of the invention include an active venting system. According to an embodiment of the invention, the active venting system may include a substrate having one or more seams formed through the substrate. In order to open the vents defined by the seams through the substrate, a piezoelectric layer may be formed proximate to one or more of the seams. Additional embodiments may include a first electrode and a second electrode that contact the piezoelectric layer in order to provide a voltage differential across the piezoelectric layer. In an embodiment the active venting system may be integrated into a garment. In such an embodiment, the garment may also include an electronics module for controlling the actuators. Additionally, conductive traces may be printed on the garment or sewn into the garment to provide electrical connections from the electronics module to each of the piezoelectric actuators.

公开(公告)号：US20190141456A1

公开(公告)日：2019-05-09

申请号：US16096568

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Johanna SWAN ,  Shawna M. LIFF ,  Thomas L. SOUNART ,  Sasha N. OSTER

IPC: H04R17/00 ,  B06B1/06

CPC classification number: H04R17/005 ,  B06B1/0622 ,  B06B1/0625 ,  B06B1/0644 ,  H04R2201/028

Abstract: Embodiments of the invention include an acoustic transducer device having a base structure that is positioned in proximity to a cavity of an organic substrate, a piezoelectric material in contact with a first electrode of the base structure, and a second electrode in contact with the piezoelectric material. In one example, for a transmit mode, a voltage signal is applied between the first and second electrodes and this causes a stress in the piezoelectric material which causes a stack that is formed with the first electrode, the piezoelectric material, and the second electrode to vibrate and hence the base structure to vibrate and generate acoustic waves.

公开(公告)号：US20180376591A1

公开(公告)日：2018-12-27

申请号：US16118990

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Yoshihiro TOMITA ,  Joshua D. HEPPNER ,  Shawna M. LIFF ,  Pramod MALATKAR

IPC: H05K1/03 ,  H05K3/00 ,  A41D13/00 ,  A43B1/00 ,  A43B3/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  A41D1/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.

公开(公告)号：US20180331051A1

公开(公告)日：2018-11-15

申请号：US15776021

申请日：2015-12-22

Applicant: Georgios C. DOGLAMIS ,  Telesphor KAMGAING ,  Eric J. LI ,  Javier A. FALCON ,  INTEL CORPORATION

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Eric J. LI, Sr. ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR ,  Shawna M. LIFF

IPC: H01L23/66 ,  H01L23/552 ,  H01L25/16 ,  H01L23/498 ,  H01L23/31

Abstract: Embodiments of the invention include a microelectronic device that includes a first die having a silicon based substrate and a second die coupled to the first die. In one example, the second die is formed with compound semiconductor materials. The microelectronic device includes a substrate that is coupled to the first die with a plurality of electrical connections. The substrate including an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20180003677A1

公开(公告)日：2018-01-04

申请号：US15199901

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Sasha N. OSTER ,  Feras EID ,  Georgios C. DOGIAMIS ,  Thomas L. SOUNART ,  Adel A. ELSHERBINI ,  Johanna M. SWAN ,  Shawna M. LIFF

IPC: G01N29/02 ,  B81B3/00 ,  G01N33/00 ,  G01N33/543 ,  G01N33/22 ,  G01N29/036

CPC classification number: G01N29/022 ,  B81B3/0021 ,  B81B2201/0214 ,  G01N29/036 ,  G01N29/2437 ,  G01N33/0047 ,  G01N33/227 ,  G01N33/54373 ,  G01N2291/0255 ,  G01N2291/0256 ,  G01N2291/0423

Abstract: Embodiments of the invention include a chemical species-sensitive device that includes an input transducer to receive input signals, a base structure that is coupled to the input transducer and positioned in proximity to a cavity of an organic substrate, a chemically sensitive functionalization material attached to the base structure, and an output transducer to generate output signals. For a chemical sensing functionality, a desired chemical species attaches to the chemically sensitive functionalization material which causes a change in mass of the base structure and this change in mass causes a change in a mechanical resonant frequency of the chemical species-sensitive device.

公开(公告)号：US20240213171A1

公开(公告)日：2024-06-27

申请号：US18596488

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Tomita YOSHIHIRO ,  Eric J. LI ,  Shawna M. LIFF ,  Javier A. FALCON ,  Joshua D. HEPPNER

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/13 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/552 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/11 ,  H01L25/16

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/19 ,  H01L24/48 ,  H01L24/96 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/16 ,  H01L24/16 ,  H01L25/042 ,  H01L25/071 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/112 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/81024 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1304 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/181 ,  H01L2924/1815

Abstract: Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.