公开(公告)号：US20200272513A1

公开(公告)日：2020-08-27

申请号：US16740794

申请日：2020-01-13

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunther ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10678319B2

公开(公告)日：2020-06-09

申请号：US16252012

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F1/32 ,  G06F15/76 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3293 ,  G06F30/34 ,  G06F119/06 ,  G06F119/08

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US10372197B2

公开(公告)日：2019-08-06

申请号：US15367330

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/32

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US10248181B2

公开(公告)日：2019-04-02

申请号：US15381241

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3293 ,  G06F1/3203 ,  G11C7/22 ,  G06F13/42 ,  G06F1/3296 ,  G06F13/40

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US10234920B2

公开(公告)日：2019-03-19

申请号：US15252543

申请日：2016-08-31

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Jorge P. Rodriguez

IPC: G06F1/32 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes: at least one core to execute instructions; a power controller to control power consumption of the processor; and a storage to store a plurality of entries to associate a dynamic capacitance with a time duration for which a current spike is to be exposed to a power delivery component. Other embodiments are described and claimed.

公开(公告)号：US20190042280A1

公开(公告)日：2019-02-07

申请号：US15936585

申请日：2018-03-27

Applicant: Intel Corporation

Inventor： Vedvyas Shanbhogue ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Russell Fenger ,  Ashok Raj ,  Kameswar Subramaniam

IPC: G06F9/445 ,  G06F11/34 ,  G06F11/30

Abstract: In one embodiment, a processor includes a plurality of cores to execute instructions, a first identification register having a first field to store a feedback indicator to indicate to an operating system (OS) that the processor is to provide hardware feedback information to the OS dynamically and a power controller coupled to the plurality of cores. The power controller may include a feedback control circuit to dynamically determine the hardware feedback information for at least one of the plurality of cores and inform the OS of an update to the hardware feedback information. Other embodiments are described and claimed.

公开(公告)号：US10037067B2

公开(公告)日：2018-07-31

申请号：US15138505

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Inder M. Sodhi ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Ryan Wells

IPC: G06F1/26 ,  G06F1/32 ,  G11C7/22 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F1/324 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F13/4068 ,  G06F13/4282 ,  G11C7/22 ,  Y02D10/122 ,  Y02D10/126 ,  Y02D10/151

Abstract: In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.

公开(公告)号：US20180088647A1

公开(公告)日：2018-03-29

申请号：US15279744

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Anupama Suryanarayanan ,  Avinash N. Ananthakrishnan ,  Chinmay Ashok ,  Jeremy J. Shrall

IPC: G06F1/26 ,  G06F1/32 ,  G06F13/42

CPC classification number: G06F1/266 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3287 ,  G06F13/4282 ,  G06F2213/0016 ,  Y02B70/16 ,  Y02D10/14 ,  Y02D10/151

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

公开(公告)号：US09417681B2

公开(公告)日：2016-08-16

申请号：US14697541

申请日：2015-04-27

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don Soltis ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F15/177 ,  G06F1/32 ,  G06F1/00 ,  G06F1/20

CPC classification number: G06F1/3243 ,  G06F1/206 ,  G06F1/28 ,  G06F1/3206 ,  Y02D10/152

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

Abstract translation: 装置的一个实施例包括具有处理器和裸片上非易失性存储资源的半导体芯片。 片上非易失性存储器可以为处理器的相同性能状态的不同配置和处理器的使用情况存储不同的适当的性能相关信息。

公开(公告)号：US09405345B2

公开(公告)日：2016-08-02

申请号：US14039193

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Stephen H. Gunther ,  Jeremy J. Shrall

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F11/30 ,  G06F1/26

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/324 ,  G06F11/3024 ,  G06F11/3058 ,  Y02D10/126 ,  Y02D10/174

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的至少一个核心和耦合到核心的功率控制器。 功率控制器可以包括功率包络控制逻辑以接收多个功率包络参数，并且使得处理器的功率消耗水平能够超过时间窗口的一部分的功率突发阈值。 该部分可以根据时间窗口的长度和占空比来确定，其中功率包络参数被编程用于包括处理器的系统，并且包括功率脉冲串阈值，时间窗口和占空比。 描述和要求保护其他实施例。