公开(公告)号：US20190189913A1

公开(公告)日：2019-06-20

申请号：US16329169

申请日：2016-09-27

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Kaan Oguz ,  Satyarth Suri ,  Kevin O'Brien ,  Mark Doczy ,  Charles Kuo

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  G11C11/16 ,  H01F10/32

CPC classification number: H01L43/10 ,  G11C11/16 ,  G11C11/161 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.

公开(公告)号：US20160242279A1

公开(公告)日：2016-08-18

申请号：US15012557

申请日：2016-02-01

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H05K1/03 ,  H05K1/02 ,  H05K3/10 ,  H05K3/32 ,  H05K3/28

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US12302643B2

公开(公告)日：2025-05-13

申请号：US17572437

申请日：2022-01-10

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Ilya Karpov ,  Brian Doyle ,  Ravi Pillarisetty ,  Abhishek Sharma

IPC: H10D89/60 ,  H10D8/00

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises the first material, wherein the second structure is between the first and third structures.

公开(公告)号：US20240114696A1

公开(公告)日：2024-04-04

申请号：US17957603

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher Neumann ,  Cory Weinstein ,  Nazila Haratipour ,  Brian Doyle ,  Sou-Chi Chang ,  Tristan Tronic ,  Shriram Shivaraman ,  Uygar Avci

IPC: H01L27/11507 ,  H01L27/11514

CPC classification number: H01L27/11507 ,  H01L27/11514

Abstract: Multiple-ferroelectric capacitor structures in memory devices, including in integrated circuit devices, and techniques for forming the structures. Insulators separating individual outer plates in a ferroelectric capacitor array are supported between wider portions of a shared, inner plate. Wider portions of an inner plate may be formed in lateral recesses between insulating layers. Ferroelectric material may be deposited over the inner plate between insulating layers after removing sacrificial layers. An etch-stop layer may protect the inner plate when sacrificial layers are removed. An etch-stop or interface layer may remain over the inner plate adjacent insulators.

公开(公告)号：US11417705B2

公开(公告)日：2022-08-16

申请号：US16147555

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Brian Doyle ,  Prashant Majhi ,  Elijah Karpov ,  Ravi Pillarisetty ,  Ashishek Sharma

IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.

公开(公告)号：US11386951B2

公开(公告)日：2022-07-12

申请号：US16022547

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Kevin O'Brien ,  Brian Doyle ,  Kaan Oguz ,  Noriyuki Sato ,  Charles Kuo ,  Mark Doczy

IPC: G11C11/56 ,  H01L43/02 ,  G11C11/16 ,  H01F10/32 ,  H01L43/10 ,  H01L27/22 ,  H01L43/12

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster has a magnetic material layer. The booster may further have an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

公开(公告)号：US20170347448A1

公开(公告)日：2017-11-30

申请号：US15676519

申请日：2017-08-14

Applicant: Intel Corporation

Inventor： Christopher Jezewski ,  Ravi Pillarisetty ,  Brian Doyle

IPC: H05K1/03 ,  D03D11/02 ,  D03D15/00 ,  H05K3/00 ,  H05K3/10 ,  H05K3/32 ,  D03D1/00 ,  H05K3/28 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/038 ,  D03D1/0088 ,  D03D11/02 ,  D03D15/00 ,  H05K1/028 ,  H05K1/0393 ,  H05K1/189 ,  H05K3/0058 ,  H05K3/10 ,  H05K3/28 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0145 ,  H05K2201/015 ,  H05K2201/0154 ,  H05K2201/0158 ,  H05K2201/029

Abstract: A system comprises an article comprising one or more fabric layers, a. plurality of electronic devices, each being incorporated into or onto one of the one or more fabric layers, and one or more communication links between two or more of the plurality of electronic devices. Each of the plurality of electronic devices can comprise a flexible substrate coupled to the fabric layer, one or more metallization layers deposited on the flexible substrate, and one or more electronic components electrically coupled to the one or more metallization layers.

公开(公告)号：US09548441B2

公开(公告)日：2017-01-17

申请号：US14659425

申请日：2015-03-16

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Mark L. Doczy ,  Brian Doyle ,  Uday Shah ,  David L. Kencke ,  Roksana Golizadeh Mojarad ,  Robert S. Chau

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L43/10 ,  G11C11/16 ,  H01F10/193 ,  H01F10/32 ,  H01L27/22 ,  H01L29/82 ,  H01F41/32

CPC classification number: H01L43/02 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/18 ,  H01F10/1933 ,  H01F10/3254 ,  H01F10/3286 ,  H01F41/325 ,  H01L27/226 ,  H01L27/228 ,  H01L29/82 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Magnetic tunnel junctions (MTJ) suitable for spin transfer torque memory (STTM) devices, include perpendicular magnetic layers and one or more anisotropy enhancing layer(s) separated from a free magnetic layer by a crystallization barrier layer. In embodiments, an anisotropy enhancing layer improves perpendicular orientation of the free magnetic layer while the crystallization barrier improves tunnel magnetoresistance (TMR) ratio with better alignment of crystalline texture of the free magnetic layer with that of a tunneling layer.

Abstract translation: 适用于自旋转移转矩存储器（STTM）器件的磁隧道结（MTJ）包括垂直磁性层和通过结晶阻挡层与自由磁性层分离的一个或多个各向异性增强层。 在实施方案中，各向异性增强层改善了自由磁性层的垂直取向，而结晶势垒改善了隧道磁阻（TMR）比，同时自由磁层的晶体结构与隧穿层的结构更好地对准。

公开(公告)号：US20160141031A1

公开(公告)日：2016-05-19

申请号：US14546061

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: G11C16/04 ,  G11C14/00 ,  G06F12/02

CPC classification number: H01L45/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C13/0007 ,  G11C13/0026 ,  G11C14/0018 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

Abstract translation: 一些实施例包括具有包括在非易失性存储单元中的存储元件，晶体管，耦合到晶体管的栅极的接入线，第一导线和第二导线的装置和方法。 存储元件可以包括位于衬底之上且位于第一和第二导电线之间的导电氧化物材料。 存储元件包括耦合到晶体管的漏极的一部分和耦合到第二导线的另一部分。 第一导线被耦合到晶体管的源极并且可以位于存取线和存储元件之间。 进入线具有在第一方向上延伸的长度并且可以位于基板和存储元件之间。 第一和第二导线具有沿第二方向延伸的长度。

公开(公告)号：US09035387B2

公开(公告)日：2015-05-19

申请号：US14089101

申请日：2013-11-25

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Brian Doyle ,  Titash Rakshit ,  Jack Kavalieros

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/7855 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for improving multi-gate device performance are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提高多栅极器件性能的装置和方法的实施例。 可以描述和要求保护其他实施例。