-
公开(公告)号：US20180300845A1
公开(公告)日：2018-10-18
申请号：US15488547
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Adam T. Lake , Guei-Yuan Lueh , Balaji Vembu , Murali Ramadoss , Prasoonkumar Surti , Abhishek R. Appu , Altug Koker , Subramaniam M. Maiyuran , Eric C. Samson , David J. Cowperthwaite , Zhi Wang , Kun Tian , David Puffer , Brian T. Lewis
Abstract: An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.
-
公开(公告)号：US20180260153A1
公开(公告)日：2018-09-13
申请号：US15786424
申请日：2017-10-17
Applicant: Intel Corporation
Inventor： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
CPC classification number: G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.
-
13.发明授权公开(公告)号：US09176565B2
公开(公告)日：2015-11-03
申请号：US13782578
申请日：2013-03-01
Applicant: Intel Corporation
Inventor： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Weissmann , Ryan Wells
CPC classification number: G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
Abstract: In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
-
公开(公告)号：US20150205344A1
公开(公告)日：2015-07-23
申请号：US14129950
申请日：2013-06-28
Applicant: INTEL CORPORATION
Inventor： Paul S. Diefenbaugh , Eugene Gorbatov , Andrew Henroid , Eric C. Samson , Barnes Cooper
IPC: G06F1/32
CPC classification number: G06F1/3234 , G06F1/3246 , G06F1/3287 , G06F9/4893 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment an apparatus includes a multiplicity of processor components; one or more device components communicatively coupled to one or more processor components of the multiplicity of processor components; and a controller comprising logic at least a portion of which is in hardware, the logic to schedule one or more forced idle periods interspersed with one or more active periods, a forced idle period spanning a duration during which the multiplicity of processor components and the one or more device components are simultaneously placed in respective idle states that define a forced idle power state during isolated sub-periods of the forced idle period. Other embodiments are disclosed and claimed.
Abstract translation: 在一个实施例中，一种装置包括多个处理器组件; 通信地耦合到多个处理器组件的一个或多个处理器组件的一个或多个设备组件; 以及控制器，其包括其硬件中的至少一部分的逻辑，用于调度一个或多个强制空闲周期的逻辑，所述强制空闲周期与一个或多个活动周期分布，跨越持续时间的强制空闲周期，在该持续时间期间多个处理器组件和一个 或更多的设备组件同时处于分别在强制空闲时段的隔离子时段期间限定强制空闲功率状态的空闲状态。 公开和要求保护其他实施例。
-
公开(公告)号：US11533683B2
公开(公告)日：2022-12-20
申请号：US17307816
申请日：2021-05-04
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
-
Patent Agency Ranking
公开(公告)号：US11372467B2
公开(公告)日：2022-06-28
申请号：US16914290
申请日：2020-06-27
Applicant: Intel Corporation
Inventor： Ahmed Abou-Alfotouh , Phani Kumar Kandula , Linda L. Hurd , Eric C. Samson , Srikrishnan Venkataraman
IPC: G06F1/32 , G06F1/3234
Abstract: A system includes multiple processors and a power controller. Each processor includes a throttling engine. The power controller is to, in response to a determination that a first power consumption level exceeds a first threshold, assert a critical signal to each throttling engine of the plurality of processors. Further, for each processor, the throttling engine of the processor is to perform a sequence of multiple throttling states while the critical signal is asserted by the power controller, where the sequence of multiple throttling states is performed according to a state machine of the throttling engine. Other embodiments are described and claimed.
-
公开(公告)号：US10999797B2
公开(公告)日：2021-05-04
申请号：US16783076
申请日：2020-02-05
Applicant: Intel Corporation
Inventor： Eric C. Samson , Murali Ramadoss , Marc Beuchat
Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.
-
18.发明申请公开(公告)号：US20180307533A1
公开(公告)日：2018-10-25
申请号：US15493698
申请日：2017-04-21
Applicant: Intel Corporation
Inventor： Kun Tian , David J. Cowperthwaite , Murali Ramadoss , Balaji Vembu , Zhi Wang , Eric C. Samson , Altug Koker , Abhishek R. Appu , Joydeep Ray
CPC classification number: G06F9/4887 , G06F9/4831 , G06T1/20 , G06T1/60 , G06T2210/52
Abstract: A mechanism is described for facilitating multi-level scheduling of workloads in computing devices. A method of embodiments, as described herein, includes facilitating multiple levels of scheduling for processing of workloads using multiple levels of queues, where the workloads are associated with a device including a processor of a computing device.
-
19.发明申请公开(公告)号：US20180137668A1
公开(公告)日：2018-05-17
申请号：US15811459
申请日：2017-11-13
Applicant: Intel Corporation
Inventor： Pietro Mercati , Raid Ayoub , Michael Kishinevsky , Eric C. Samson , Marc Beuchat , Francesco Paterna
CPC classification number: G06T15/005 , G06F1/206 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F8/41 , G06F8/65 , G06T15/80 , Y02D10/126 , Y02D10/16 , Y02D10/171 , Y02D10/172 , Y02D10/42
Abstract: Methods and apparatus relating to techniques for dynamically selecting optimum graphics logic frequency and/or graphics logic power gating configuration are described. In an embodiment, multi-rate control logic determines processor active slice count and processor frequency based at least in part on a target Frames Per Second (FPS) value and a current FPS value. The multi-rate control logic includes slow rate control logic to determine slice gating and operating frequency and a fast rate control logic to determine operating frequency of the processor. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US09852714B2
公开(公告)日：2017-12-26
申请号：US14747682
申请日：2015-06-23
Applicant: Intel Corporation
Inventor： Eric C. Samson
CPC classification number: G09G5/18 , G06F1/324 , G09G5/363 , G09G2310/08 , G09G2330/021 , G09G2360/02 , G09G2360/12
Abstract: Systems and methods of adjusting a frequency of a graphics controller may include a logic to determine a metric associated with an input/output (I/O) queue. The metric may be used to determine whether an I/O limited condition exists. The I/O limited condition may be associated with a graphics controller. There may be a logic to cause a frequency of the graphics controller to be decreased when the I/O limited condition exists, and a logic to cause the frequency of the graphics controller to be increased when the I/O limited condition does not exist. The I/O limited condition may exist when a magnitude of the metric is equal to or greater than a first threshold. The I/O limited condition may not exist when the magnitude of the metric is equal to or less than a second threshold.
-
-
-
-
-
-
-
-
-
Search Results
55
records
(took 0.018 seconds)
