公开(公告)号：US10467011B2

公开(公告)日：2019-11-05

申请号：US14336596

申请日：2014-07-21

Applicant: Intel Corporation

Inventor： Lihu Rappoport ,  Zeev Sperber ,  Michael Mishaeli ,  Stanislav Shwartsman ,  Lev Makovsky ,  Adi Yoaz ,  Ofer Levy

IPC: G06F9/38 ,  G06F9/30

Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

公开(公告)号：US09471088B2

公开(公告)日：2016-10-18

申请号：US13925986

申请日：2013-06-25

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Efraim Rotem ,  Julius Mandelblat ,  Alexander Lyakhov ,  Larisa Novakovsky ,  George Leifman ,  Lev Makovsky ,  Ariel Sabba ,  Niv Tokman

IPC: G06F1/08 ,  G06F1/04 ,  G06F1/32

CPC classification number: G06F1/08 ,  G06F1/04 ,  G06F1/32

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, a restriction logic to receive a restriction command and to reduce delivery of the first clock signal to at least one of the plurality of units. The restriction logic may cause the first clock signal to be distributed to the plurality of units at a lower frequency than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括用于执行指令的核心，其中核心包括时钟生成逻辑，用于接收和分配第一时钟信号到核心的多个单元，用于接收限制命令并减少传送的限制逻辑 的第一时钟信号发送到多个单元中的至少一个。 限制逻辑可以使得第一时钟信号以比第一时钟信号的频率低的频率被分配到多个单元。 描述和要求保护其他实施例。

公开(公告)号：US20160019063A1

公开(公告)日：2016-01-21

申请号：US14336596

申请日：2014-07-21

Applicant: Intel Corporation

Inventor： Lihu Rappoport ,  Zeev Sperber ,  Michael Mishaeli ,  Stanislav Shwartsman ,  Lev Makovsky ,  Adi Yoaz ,  Ofer Levy

IPC: G06F9/30

CPC classification number: G06F9/3851 ,  G06F9/30 ,  G06F9/30058 ,  G06F9/3009

Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

Abstract translation: 一个方面的处理器包括解码单元，用于对来自第一线程的线程暂停指令进行解码。 处理器的后端部分与解码单元耦合。 响应于线程暂停指令，处理器的后端部分是暂停用于执行的第一线程的后续指令的处理。 随后的指令以程序顺序发生在线程暂停指令之后。 响应于线程暂停指令，后端部分还将保持处理器的后端部分的至少大部分，除了线程暂停指令之外的第一线程的指令，预定的 一段的时间。 大多数可以包括多个执行单元和指令队列单元。