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    Technologies for switching network traffic in a data center
    11.
    发明授权
    Technologies for switching network traffic in a data center 有权

    公开(公告)号：US10045098B2

    公开(公告)日：2018-08-07

    申请号：US15395203

    申请日：2016-12-30

    Applicant: Intel Corporation

    Inventor： Matthew Adiletta ,  Aaron Gorius ,  Myles Wilde ,  Michael Crocker

    IPC: H04J14/00 ,  H04Q11/00

    Abstract: Technologies for switching network traffic include a network switch. The network switch includes one or more processors and communication circuitry coupled to the one or more processors. The communication circuity is capable of switching network traffic of multiple link layer protocols. Additionally, the network switch includes one or more memory devices storing instructions that, when executed, cause the network switch to receive, with the communication circuitry through an optical connection, network traffic to be forwarded, and determine a link layer protocol of the received network traffic. The instructions additionally cause the network switch to forward the network traffic as a function of the determined link layer protocol. Other embodiments are also described and claimed.

    Three dimensional circuit systems and methods having memory hierarchies
    19.
    发明授权
    Three dimensional circuit systems and methods having memory hierarchies 有权

    公开(公告)号：US11789641B2

    公开(公告)日：2023-10-17

    申请号：US17349592

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC: G06F3/06

    CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

    Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

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