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    Interconnect structure for a microelectronic device
    11.
    发明授权
    Interconnect structure for a microelectronic device 有权

    公开(公告)号：US10366968B2

    公开(公告)日：2019-07-30

    申请号：US15282855

    申请日：2016-09-30

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

    INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE
    14.
    发明申请
    INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20190333886A1

    公开(公告)日：2019-10-31

    申请号：US16505307

    申请日：2019-07-08

    Applicant: Intel IP Corporation

    Inventor： Klaus Reingruber ,  Andreas Wolter ,  Georg Seidemann ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L25/11

    Abstract: A microelectronic package with two semiconductor die coupled on opposite sides of a redistribution layer 108, and at least partially overlapping with one another. At least a first of the semiconductor die includes two sets of contacts, the first group of contacts arranged at a lesser pitch relative to one another than are a second group of contacts. The first group of contacts at the larger pitch are placed to engage contacts in a redistribution layer 108. The second group of contacts at the lesser pitch are placed to engage respective contacts at the same pitch on the second semiconductor die.

    Fan out package-on-package with adhesive die attach
    17.
    发明授权
    Fan out package-on-package with adhesive die attach 有权

    公开(公告)号：US11380616B2

    公开(公告)日：2022-07-05

    申请号：US15981830

    申请日：2018-05-16

    Applicant: Intel IP Corporation

    Inventor： David O'Sullivan ,  Bernd Waidhas ,  Thomas Huber

    IPC: H01L23/522 ,  H01L23/538 ,  H01L23/28 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

    Abstract: Fan Out Package-On-Package (PoP) assemblies in which a second chip is adhered to a non-active side of a first chip. An active side of the first chip embedded in a first package material may be electrically coupled through one or more redistribution layers that fan out to package interconnects on a first side of the POP. A second chip may be adhered, with a second package material, to the non-active side of the first chip. An active side of the second chip may be electrically coupled to the package interconnects through a via structure extending through the first package material. Second interconnects between the second chip, or a package thereof, may contact the via structure. Use of the second package material as an adhesive may improve positional stability of the second chip to facilitate wafer-level assembly techniques.

    Molded substrate package in fan-out wafer level package
    19.
    发明授权
    Molded substrate package in fan-out wafer level package 有权

    公开(公告)号：US10720393B2

    公开(公告)日：2020-07-21

    申请号：US16458675

    申请日：2019-07-01

    Applicant: Intel IP Corporation

    Inventor： Lizabeth Keser ,  Thomas Ort ,  Thomas Wagner ,  Bernd Waidhas

    IPC: H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

    Abstract: An electronic device may include a semiconductor die. The electronic device may include a first routing layer. The first routing layer may be coupled to the semiconductor die. A first plurality of routing traces may be in electrical communication with the semiconductor die. The first plurality of routing traces may be positioned within a first routing footprint. The first routing footprint may have a width greater than a width of the semiconductor die.A second routing layer may be coupled to the first routing layer. A second plurality of routing traces may be in electrical communication with the first plurality of routing traces. The second plurality of routing traces may be positioned within a second routing footprint. The second routing footprint may have a width greater than the width of the first routing footprint.

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