公开(公告)号：US10347582B2

公开(公告)日：2019-07-09

申请号：US16136635

申请日：2018-09-20

Applicant: Invensas Corporation

Inventor： Belgacem Haba

IPC: H01L23/538 ,  H01L21/48 ,  H01L25/065 ,  H01L23/00

Abstract: Embedded vialess bridges are provided. In an implementation, discrete pieces containing numerous conduction lines or wires in a 3-dimensional bridge piece are embedded where needed in a main substrate to provide dense arrays of signal, power, and electrical ground wires below the surface of the main substrate. Vertical conductive risers to reach the surface plane of the main substrate are also included in the discrete piece, for connecting to dies on the surface of the substrate and thereby interconnecting the dies to each other through the dense array of wires in the discrete piece. The discrete piece to be embedded may have parallel planes of conductors at regular intervals within itself, and thus may present a working surface homogeneously covered with the ends of vertical conductors available to connect surface components to each other and to ground and power at many places along the embedded piece.

公开(公告)号：US10290612B1

公开(公告)日：2019-05-14

申请号：US15993271

申请日：2018-05-30

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Javier A. Delacruz

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/78

Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.

公开(公告)号：US20180331074A1

公开(公告)日：2018-11-15

申请号：US16037453

申请日：2018-07-17

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Wael Zohni ,  Belgacem Haba ,  Frank Lambrecht

IPC: H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  G11C5/04 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/04 ,  G11C5/063 ,  G11C5/066 ,  G11C8/18 ,  H01L23/02 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/49113 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/3011 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/85

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

公开(公告)号：US10109903B2

公开(公告)日：2018-10-23

申请号：US15287056

申请日：2016-10-06

Applicant: Invensas Corporation

Inventor： Shaowu Huang ,  Belgacem Haba

IPC: H05K1/18 ,  H01P1/203 ,  H01P11/00 ,  H05K1/02 ,  H05K1/16 ,  H05K3/46

Abstract: Flipped radio frequency (RF) and microwave filters and components for compact package assemblies are provided. An example RF filter is constructed by depositing a conductive trace, such as a redistribution layer, onto a flat surface of a substrate, to form an RF filter element. The substrate is vertically mounted on a motherboard, thereby saving dedicated area. Multiple layers of substrate are laminated into a stack and mounted so that the RF filter elements of each layer are in vertical planes with respect to a horizontal motherboard, providing dramatic reduction in size. Deposited conductive traces of an example flipped RF filter stack provide various stub configurations of an RF filter and emulate various distributed filter elements and their configuration geometries. The deposited conductive traces also form other electronic components to be used in conjunction with the RF filter elements. A wirebond or bond via array (BVATM) version provides flipped RF and microwave filters.

公开(公告)号：US10103094B2

公开(公告)日：2018-10-16

申请号：US15626687

申请日：2017-06-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H05K1/00 ,  H01L23/498 ,  H01L23/48 ,  H01L23/36 ,  H01L23/373 ,  H01L21/768 ,  H01L23/367

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.

公开(公告)号：US10032751B2

公开(公告)日：2018-07-24

申请号：US15247705

申请日：2016-08-25

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Arkalgud R. Sitaram

IPC: H01L21/30 ,  H01L21/46 ,  H01L25/065 ,  H01L21/02 ,  H01L21/311 ,  H01L23/00 ,  H01L25/00 ,  H01L23/64

Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants κ of the dielectric materials employed in the ultrathin layer and their respective thicknesses. Electrical and grounding connections can be made at the edge of the coupled stack.

公开(公告)号：US10015881B2

公开(公告)日：2018-07-03

申请号：US14573461

申请日：2014-12-17

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Craig Mitchell ,  Belgacem Haba ,  Ilyas Mohammed

IPC: H01K3/10 ,  H05K1/02 ,  H01R12/71 ,  H05K3/42 ,  H01L23/498 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L23/49827 ,  H01L2924/0002 ,  H01R12/714 ,  H05K1/114 ,  H05K1/115 ,  H05K3/42 ,  H05K2201/09645 ,  H05K2201/10378 ,  H05K2203/0242 ,  H05K2203/025 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method is disclosed for making an interconnection component. The steps include forming a mask layer covering a first opening in a sheet-like element that has first and second opposed surfaces; forming a plurality of mask openings in the mask layer, wherein the first opening and a portion of the first surface are partly aligned with each mask opening; and forming electrical conductors on spaced apart portions of the first surface and on spaced apart portions of the interior surface within the first opening which are exposed by the mask openings. The element may consist essentially of a material having a coefficient of thermal expansion of less than 10 parts per million per degree Celsius. Each conductor may extend along an axial direction of the first opening and the first conductors may be fully separated from one another within the first opening.

公开(公告)号：US09985007B2

公开(公告)日：2018-05-29

申请号：US15393083

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/10 ,  H01L25/00 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with multiple levels and methods therefor are disclosed. In a PoP device, a first integrated circuit die is surface mount coupled to an upper surface of a package substrate. First and second conductive lines are coupled to the upper surface of the package substrate respectively at different heights in a fan-out region. A first molding layer is formed over the upper surface of the package substrate. A first and a second wafer-level packaged microelectronic component are located above an upper surface of the first molding layer respectively surface mount coupled to a first and a second set of upper portions of the first conductive lines. A third and a fourth wafer-level packaged microelectronic component are located above the first and the second wafer-level packaged microelectronic component respectively surface mount coupled to a first and a second set of upper portions of the second conductive lines.

公开(公告)号：US09972609B2

公开(公告)日：2018-05-15

申请号：US15393112

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Package-on-package (“PoP”) devices with WLP (“WLP”) components with dual RDLs (“RDLs”) for surface mount dies and methods therefor. In a PoP, a first IC die surface mount coupled to an upper surface of a package substrate. Conductive lines are coupled to the upper surface of the package substrate in a fan-out region. A molding layer is formed over the upper surface of the package substrate. A first and a second WLP microelectronic component are located at a same level above an upper surface of the molding layer respectively surface mount coupled to sets of upper portions of the conductive lines. Each of the first and the second WLP microelectronic components have a second IC die located between a first RDL and a second RDL. A third and a fourth IC die are respectively surface mount coupled over the first and the second WLP microelectronic components.

公开(公告)号：US09972573B2

公开(公告)日：2018-05-15

申请号：US15393048

申请日：2016-12-28

Applicant: Invensas Corporation

Inventor： Min Tao ,  Hoki Kim ,  Ashok S. Prabhu ,  Zhuowen Sun ,  Wael Zohni ,  Belgacem Haba

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/52 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/5283 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/09 ,  H01L24/46 ,  H01L24/49 ,  H01L24/83 ,  H01L25/0652 ,  H01L25/071 ,  H01L25/105 ,  H01L25/112 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02379 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15151 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/19107

Abstract: Wafer-level packaged components are disclosed. In a wafer-level-packaged, an integrated circuit die has first contacts in an inner third region of a surface of the integrated circuit die. A redistribution layer has second contacts in an inner third region of a first surface of the redistribution layer and third contacts in an outer third region of a second surface of the redistribution layer opposite the first surface thereof. The second contacts of the redistribution layer are coupled for electrical conductivity to the first contacts of the integrated circuit die with the surface of the integrated circuit die face-to-face with the first surface of the redistribution layer. The third contacts are offset from the second contacts for being positioned in a fan-out region for association at least with the outer third region of the second surface of the redistribution layer, the third contacts being surface mount contacts.