公开(公告)号：US20170171003A1

公开(公告)日：2017-06-15

申请号：US15441783

申请日：2017-02-24

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Cyprian Emeka Uzoh ,  Yong Chen

IPC: H04L27/01 ,  H01L25/065 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/53238 ,  H01L23/53295 ,  H01L23/5384 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/02372 ,  H01L2224/11 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.

公开(公告)号：US09640236B2

公开(公告)日：2017-05-02

申请号：US14645811

申请日：2015-03-12

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen

IPC: G11C8/06 ,  G11C5/06 ,  G11C8/12 ,  G06F12/00 ,  G11C5/04

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F12/0623 ,  G06F13/1694 ,  G11C5/04 ,  G11C5/06 ,  G11C8/06 ,  G11C8/12 ,  H01L2224/4824 ,  H01L2924/15311

Abstract: An apparatus for reducing load in a memory module. In such an apparatus, there is a circuit platform with a plurality of memory chips coupled to the circuit platform. Each memory chip of the plurality of memory chips each has a plurality of memory dies. At least one controller is coupled to the circuit platform and further coupled to the plurality of memory chips for communication with the plurality of memory dies thereof. The at least one controller is for receiving chip select signals to provide a plurality of rank select signals in excess of the chip select signals. The plurality of memory dies are coupled with wire bonds within the plurality of memory chips for a reduced load for coupling the circuit platform for communicating via a memory channel. The load is sufficiently reduced for having at least two instances of the memory module share the memory channel.

公开(公告)号：US09343398B2

公开(公告)日：2016-05-17

申请号：US14497825

申请日：2014-09-26

Applicant: Invensas Corporation

Inventor： Yong Chen ,  Zhuowen Sun ,  Kyong-Mo Bang

IPC: H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/181 ,  H05K1/0262 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09336 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a substrate and a microelectronic element. The substrate can include terminals comprising at least first power terminals and other terminals in an area array at a surface of the substrate. The substrate can also include a power plane element electrically coupled to the first power terminals. The area array can have a peripheral edge and a continuous gap between the terminals extending inwardly from the peripheral edge in a direction parallel to the surface. The terminals on opposite sides of the gap can be spaced from one another by at least 1.5 times a minimum pitch of the terminals. The power plane element can extend within the gap from at least the peripheral edge at least to the first power terminals. Each first power terminal can be separated from the peripheral edge by two or more of the other terminals.

Abstract translation: 微电子封装可以包括衬底和微电子元件。 衬底可以包括在衬底的表面处的区域阵列中至少包括第一电源端子和其他端子的端子。 基板还可以包括电耦合到第一电源端子的功率平面元件。 区域阵列可以具有周边边缘和在平行于表面的方向上从周边边缘向内延伸的端子之间的连续间隙。 间隙的相对侧上的端子可以彼此间隔开至少1.5倍的端子的最小间距。 功率平面元件可以在间隙内从至少外围边缘至少延伸到第一电源端子。 每个第一电源端子可以通过两个或更多其它端子与外围边缘分离。

公开(公告)号：US20150302901A1

公开(公告)日：2015-10-22

申请号：US14753607

申请日：2015-06-29

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/02 ,  G11C5/06 ,  G11C11/408 ,  G11C5/04

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。

公开(公告)号：US20140362629A1

公开(公告)日：2014-12-11

申请号：US14075020

申请日：2013-11-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/02

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。

公开(公告)号：US20170133081A1

公开(公告)日：2017-05-11

申请号：US15337323

申请日：2016-10-28

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: G11C11/408 ,  H01L25/18 ,  G11C11/409 ,  H01L23/64 ,  G11C5/06 ,  H01L25/065 ,  H01L23/02

CPC classification number: G11C11/4087 ,  G11C5/063 ,  G11C8/18 ,  G11C11/409 ,  H01L23/02 ,  H01L23/3128 ,  H01L23/64 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic assembly can include an address bus comprising a plurality of signal conductors each passing sequentially through first, second, third, and fourth connection regions, and first and second microelectronic packages. The first microelectronic package can include first and second microelectronic elements, and the second microelectronic package can include third and fourth microelectronic elements. Each microelectronic element can be electrically coupled to the address bus via the respective connection region. An electrical characteristic between the first and second connection regions can be within a same tolerance of the electrical characteristic between the second and third connection regions.

公开(公告)号：US09640282B1

公开(公告)日：2017-05-02

申请号：US14980189

申请日：2015-12-28

Applicant: Invensas Corporation

Inventor： Yong Chen ,  Zhuowen Sun

IPC: G11C29/00 ,  G11C29/56 ,  G11C29/12

CPC classification number: G11C29/1201 ,  G11C29/48 ,  G11C2029/1206 ,  G11C2029/2602 ,  G11C2229/743 ,  H01L2224/32145 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012

Abstract: A method of testing a microelectronic package configured to provide memory access can include energizing terminals of the microelectronic package, the terminals including first terminals configured to carry address information and second terminals configured to carry data signals. The method can also include applying read and write test data signals simultaneously to the first and second sets of second terminals, so as to simultaneously test read and write operation in first and second microelectronic elements of the microelectronic package. The first and second microelectronic elements can be configured to provide access to memory storage array locations in the first and second microelectronic elements. The terminals can also include third terminals configured to receive a test mode input that reconfigures the first and second microelectronic elements to permit simultaneous access to memory storage array locations in the first and second microelectronic elements.

公开(公告)号：US20160035703A1

公开(公告)日：2016-02-04

申请号：US14448040

申请日：2014-07-31

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/0657 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00015

Abstract: A microelectronic package can include a substrate comprising a dielectric element having first and second opposite surfaces, and a microelectronic element having a face extending parallel to the first surface. The substrate can also include a plurality of peripheral edges extending between the first and second surfaces defining a generally rectangular or square periphery of the substrate. The substrate can further include a plurality of contacts and terminals, the contacts being at the first surface, the terminals being at at least one of the first or second surfaces. The microelectronic elements can have a plurality of edges bounding the face, and a plurality of element contacts at the face electrically coupled with the terminals through the contacts of the substrate. Each edge of the microelectronic element can be oriented at an oblique angle with respect to the peripheral edges of the substrate.

Abstract translation: 微电子封装可以包括包括具有第一和第二相对表面的电介质元件的基板和具有平行于第一表面延伸的面的微电子元件。 衬底还可以包括在第一和第二表面之间延伸的多个外围边缘，其限定基底的大致矩形或正方形的周边。 所述基板还可包括多个触点和端子，所述触点位于所述第一表面处，所述端子处于所述第一或第二表面中的至少一个。 微电子元件可以具有限定该面的多个边缘，并且在该表面处的多个元件触点通过基板的触点与端子电耦合。 微电子元件的每个边缘可以相对于衬底的周边边缘倾斜地定向。

公开(公告)号：US09070423B2

公开(公告)日：2015-06-30

申请号：US14075020

申请日：2013-11-08

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Yong Chen ,  Belgacem Haba ,  Wael Zohni ,  Zhuowen Sun

IPC: G11C5/00 ,  G11C5/02 ,  G11C8/00 ,  G11C8/18 ,  H01L23/00 ,  H01L25/065 ,  G11C5/04 ,  G11C5/06 ,  G11C8/12 ,  H01L23/538

CPC classification number: G11C5/025 ,  G11C5/04 ,  G11C5/063 ,  G11C8/12 ,  G11C11/408 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic package can include a support element having first and second surfaces and substrate contacts at the first or second surface, zeroth and first stacked microelectronic elements electrically coupled with the substrate contacts, and terminals at the second surface electrically coupled with the microelectronic elements. The second surface can have a southwest region encompassing entire lengths of south and west edges of the second surface and extending in orthogonal directions from the south and west edges one-third of each distance toward north and east edges of the second surface, respectively. The terminals can include first terminals at a southwest region of the second surface, the first terminals configured to carry address information usable by circuitry within the microelectronic package to determine an addressable memory location from among all the available addressable memory locations of the memory storage arrays of at least one of the zeroth or first microelectronic elements.

Abstract translation: 微电子封装可以包括具有第一和第二表面的第一表面和第二表面的支撑元件以及与第一表面或第二表面的第一和第二堆叠的微电子元件，以及与第二表面电连接的第二表面的端子与微电子元件电耦合。 第二表面可以具有包括第二表面的南部和西部边缘的整个长度的西南区域，并且在从每个距离的南部和西部边缘的正交方向上分别向第二表面的北部和东部边缘延伸。 终端可以包括在第二表面的西南区域的第一终端，第一终端被配置为携带可用于微电子封装内的电路的地址信息，以从存储器存储阵列的所有可寻址的存储器位置中确定可寻址存储器位置 第一或第一微电子元件中的至少一个。

公开(公告)号：US10103093B2

公开(公告)日：2018-10-16

申请号：US15441783

申请日：2017-02-24

Applicant: Invensas Corporation

Inventor： Zhuowen Sun ,  Cyprian Emeka Uzoh ,  Yong Chen

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L23/532 ,  H01L23/00

Abstract: An apparatus relating generally to a substrate is disclosed. In such an apparatus, the substrate has a first surface and a second surface opposite the first surface. The first surface and the second surface define a thickness of the substrate. A via structure extends from the first surface of the substrate to the second surface of the substrate. The via structure has a first terminal at or proximate to the first surface and a second terminal at or proximate to the second surface provided by a conductive member of the via structure extending from the first terminal to the second terminal. A barrier layer of the via structure is disposed between at least a portion of the conductive member and the substrate. The barrier layer has a conductivity configured to offset a capacitance between the conductive member and the substrate when a signal is passed through the conductive member of the via structure.