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    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING
    13.
    发明申请
    NOVEL HIGH-K METAL GATE STRUCTURE AND METHOD OF MAKING 审中-公开
    新型高K金属结构及其制备方法

    公开(公告)号：US20100044804A1

    公开(公告)日：2010-02-25

    申请号：US12427222

    申请日：2009-04-21

    Applicant: Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    Inventor： Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    IPC: H01L29/78 ,  H01L21/28

    CPC classification number: H01L21/28088 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

    Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，形成在衬底中的晶体管，晶体管包括形成在衬底上的高k栅极电介质，高k栅极电介质具有从一个侧壁到 高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极，金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度，第二长度小于 第一长。

    Method of fabricating a TFT-LCD
    17.
    发明授权
    Method of fabricating a TFT-LCD 失效
    制造TFT-LCD的方法

    公开(公告)号：US06063653A

    公开(公告)日：2000-05-16

    申请号：US111279

    申请日：1998-07-07

    Applicant: Kang-Cheng Lin ,  Gwo-Long Lin

    Inventor： Kang-Cheng Lin ,  Gwo-Long Lin

    IPC: G03F7/20 ,  H01L21/336 ,  H01L21/84

    CPC classification number: G03F7/2022 ,  H01L29/66765

    Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned. A further dielectric layer for isolation is formed on the patterned amorphous silicon layer. Source and drain are patterned on the dielectric layer to contact with the amorphous silicon layer. Subsequently, a passivation layer is deposited on the source and drain.

    Abstract translation: 本发明包括在玻璃基板上图案化金属层。 在金属层上形成电介质层。 随后在电介质层上形成非晶硅层。 在非晶硅层上形成第一正性光致抗蚀剂。 然后，通过使用栅电极作为掩模来使用背面曝光。 进行烘烤步骤以扩展光致抗蚀剂的下部。 接下来，在非晶硅层和残留的第一正性光致抗蚀剂层上形成第二正性光致抗蚀剂层。 使用栅极电极作为掩模，再次从衬底的背面再次进行背面曝光。 应用第二后续步骤来扩展第二正性光致抗蚀剂层的下部。 通过使用第二正性光致抗蚀剂作为掩模来进行离子注入。 接着，将基板退火。 然后将非晶硅层图案化。 在图案化的非晶硅层上形成用于隔离的另外的电介质层。 源极和漏极在电介质层上被图案化以与非晶硅层接触。 随后，钝化层沉积在源极和漏极上。

    Method for forming a thin film transistor
    18.
    发明授权
    Method for forming a thin film transistor 失效
    薄膜晶体管的形成方法

    公开(公告)号：US5834071A

    公开(公告)日：1998-11-10

    申请号：US802344

    申请日：1997-02-11

    Applicant: Kang-Cheng Lin

    Inventor： Kang-Cheng Lin

    IPC: H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  B05D3/06

    CPC classification number: H01L29/66765 ,  H01L21/2026 ,  H01L29/78675

    Abstract: Method for forming a polycrystalline silicon (ploy-Si) film of a semiconductor device includes forming the gate electrode on a substrate and depositing a dielectric layer on the substrate and the conductive layer. Then a first layer (microcrystalline silicon:.mu.c-Si) is formed on the dielectric layer and a second layer (hydrogenated amorphous silicon:a-Si:H) is deposited on the first layer. Noted that the polycrystalline silicon (poly-Si) can be fabricated by applying the laser annealing to the first layer and the second layer to transform them to poly-Si. Annealing the first layer and the second layer by laser, followed by fabricating the source and drain electrodes, thus the TFT with good electrical characteristics is fabricated.

    Abstract translation: 用于形成半导体器件的多晶硅（合金-Si）膜的方法包括在衬底上形成栅电极并在衬底和导电层上沉积电介质层。 然后在电介质层上形成第一层（微晶硅:μc-Si），在第一层上沉积第二层（氢化非晶硅：a-Si：H）。 注意到可以通过对第一层和第二层施加激光退火来将其转变成多晶硅来制造多晶硅（poly-Si）。 通过激光退火第一层和第二层，随后制造源极和漏极，由此制造具有良好电特性的TFT。

    Method of fabricating dual high-k metal gate for MOS devices
    19.
    发明授权
    Method of fabricating dual high-k metal gate for MOS devices 有权
    制造用于MOS器件的双高k金属栅极的方法

    公开(公告)号：US08853068B2

    公开(公告)日：2014-10-07

    申请号：US13329877

    申请日：2011-12-19

    Applicant: Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    Inventor： Peng-Fu Hsu ,  Kang-Cheng Lin ,  Kuo-Tai Huang

    IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/8238

    CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/49 ,  H01L29/51

    Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.

    Abstract translation: 本公开提供了制造半导体器件的方法。 该方法包括提供具有第一区域和第二区域的半导体衬底，在半导体衬底上形成高k电介质层，在第一区域的高k电介质层上形成覆盖层，形成第一金属层 在第一区域中的覆盖层和第二区域中的高k电介质之上，然后在第一区域中形成第一栅极堆叠，在第二区域中形成第二栅极叠层，保护第一栅极叠层中的第一金属层，同时 对所述第二栅极堆叠中的所述第一金属层进行处理工艺，以及在所述第一栅极堆叠中的所述第一金属层上方以及所述第二栅极堆叠中经处理的第一金属层之上形成第二金属层。

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