公开(公告)号：US06063653A

公开(公告)日：2000-05-16

申请号：US111279

申请日：1998-07-07

Applicant: Kang-Cheng Lin ,  Gwo-Long Lin

Inventor： Kang-Cheng Lin ,  Gwo-Long Lin

IPC: G03F7/20 ,  H01L21/336 ,  H01L21/84

CPC classification number: G03F7/2022 ,  H01L29/66765

Abstract: The present invention includes patterning a metal layer on a glass substrate. A dielectric layer is formed on the metal layer. An amorphous silicon layer is subsequently formed on the dielectric layer. A first positive photoresist is formed on the amorphous silicon layer. Then, a back-side exposure is used by using the gate electrodes as a mask. A bake step is performed to expand the lower portion of the photoresist. Next, a second positive photoresist layer is formed on the amorphous silicon layer and the residual first positive photoresist layer. A further back-side exposure is employed again from the back side of the substrate using the gate electrode as the mask. A second back step is applied to expand the lower portion of the second positive photoresist layer. An ion implantation is performed by using the second positive photoresist as a mask. Next, the substrate is then annealed. Amorphous silicon layer is then patterned. A further dielectric layer for isolation is formed on the patterned amorphous silicon layer. Source and drain are patterned on the dielectric layer to contact with the amorphous silicon layer. Subsequently, a passivation layer is deposited on the source and drain.

Abstract translation: 本发明包括在玻璃基板上图案化金属层。 在金属层上形成电介质层。 随后在电介质层上形成非晶硅层。 在非晶硅层上形成第一正性光致抗蚀剂。 然后，通过使用栅电极作为掩模来使用背面曝光。 进行烘烤步骤以扩展光致抗蚀剂的下部。 接下来，在非晶硅层和残留的第一正性光致抗蚀剂层上形成第二正性光致抗蚀剂层。 使用栅极电极作为掩模，再次从衬底的背面再次进行背面曝光。 应用第二后续步骤来扩展第二正性光致抗蚀剂层的下部。 通过使用第二正性光致抗蚀剂作为掩模来进行离子注入。 接着，将基板退火。 然后将非晶硅层图案化。 在图案化的非晶硅层上形成用于隔离的另外的电介质层。 源极和漏极在电介质层上被图案化以与非晶硅层接触。 随后，钝化层沉积在源极和漏极上。

公开(公告)号：US20130104956A1

公开(公告)日：2013-05-02

申请号：US13493379

申请日：2012-06-11

Applicant: Ming-Tzu Chou ,  Chien-Wen Chen ,  Ching-Hao Tu ,  Chih-Chiang Huang ,  Kang-Cheng Lin

Inventor： Ming-Tzu Chou ,  Chien-Wen Chen ,  Ching-Hao Tu ,  Chih-Chiang Huang ,  Kang-Cheng Lin

IPC: H01L31/05 ,  H01L31/0224

CPC classification number: H01L31/022433 ,  H01L31/0504 ,  Y02E10/50

Abstract: A solar cell module includes multiple solar cells connected in series through wiring units. Each solar cell comprises an electrode unit disposed on a photoelectric conversion unit converting solar energy into electrical energy, and including multiple finger electrodes. At least one finger electrode has a first conducting section connected to a bus bar electrode, and a second conducting section disposed on one side of the first conducting section, extending away from the bus bar electrode and having a thickness greater than that of each of the first conducting section and the bus bar electrode.

Abstract translation: 太阳能电池模块包括通过布线单元串联连接的多个太阳能电池。 每个太阳能电池包括设置在光电转换单元上的电极单元，其将太阳能转换成电能，并且包括多个指状电极。 至少一个指状电极具有连接到母线电极的第一导电部分和设置在第一导电部分的一侧上的第二导电部分，其远离母线电极延伸，并且具有大于 第一导电段和母线电极。

公开(公告)号：US20100052076A1

公开(公告)日：2010-03-04

申请号：US12270311

申请日：2008-11-13

Applicant: Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

Inventor： Da-Yuan Lee ,  Chien-Hao Huang ,  Chi-Chun Chen ,  Kang-Cheng Lin

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L29/513 ,  H01L21/823828 ,  H01L29/4966 ,  H01L29/518

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, and a transistor formed in the substrate. The transistor has a gate structure that includes an interfacial layer formed on the substrate, a high-k dielectric layer formed on the interfacial layer, a capping layer formed on the high-k dielectric layer, the capping layer including a silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof, and a polysilicon layer formed on the capping layer.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管具有栅极结构，该栅极结构包括形成在衬底上的界面层，形成在界面层上的高k电介质层，形成在高k电介质层上的覆盖层，覆盖层包括氧化硅，氮氧化硅 ，氮化硅或其组合，以及形成在覆盖层上的多晶硅层。

公开(公告)号：US6140220A

公开(公告)日：2000-10-31

申请号：US349843

申请日：1999-07-08

Applicant: Kang-Cheng Lin

Inventor： Kang-Cheng Lin

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76831 ,  H01L21/76808 ,  H01L21/76843 ,  H01L2221/1031

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

公开(公告)号：US08836038B2

公开(公告)日：2014-09-16

申请号：US12883241

申请日：2010-09-16

Applicant: Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

Inventor： Yong-Tian Hou ,  Peng-Fu Hsu ,  Jin Ying ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Tze-Liang Lee

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/823842 ,  H01L21/28044 ,  H01L21/28088 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a first MOS device of a first conductivity type and a second MOS device of a second conductivity type opposite the first conductivity type. The first MOS device includes a first gate dielectric on a semiconductor substrate; a first metal-containing gate electrode layer over the first gate dielectric; and a silicide layer over the first metal-containing gate electrode layer. The second MOS device includes a second gate dielectric on the semiconductor substrate; a second metal-containing gate electrode layer over the second gate dielectric; and a contact etch stop layer having a portion over the second metal-containing gate electrode layer, wherein a region between the portion of the contact etch stop layer and the second metal-containing gate electrode layer is substantially free from silicon.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括第一导电类型的第一MOS器件和与第一导电类型相反的第二导电类型的第二MOS器件。 第一MOS器件包括在半导体衬底上的第一栅极电介质; 在所述第一栅极电介质上的第一含金属的栅电极层; 以及位于第一含金属栅电极层上的硅化物层。 第二MOS器件包括半导体衬底上的第二栅极电介质; 在所述第二栅极电介质上方的第二含金属的栅电极层; 以及具有位于所述第二含金属栅电极层上的部分的接触蚀刻停止层，其中所述接触蚀刻停止层的所述部分和所述第二含金属栅电极层之间的区域基本上不含硅。

公开(公告)号：US08541264B2

公开(公告)日：2013-09-24

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/82

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US08450161B2

公开(公告)日：2013-05-28

申请号：US13465551

申请日：2012-05-07

Applicant: Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

Inventor： Chien-Hao Chen ,  Hao-Ming Lien ,  Ssu-Yu Li ,  Jun-Lin Yeh ,  Kang-Cheng Lin ,  Kuo-Tai Huang ,  Chii-Horng Li ,  Chien-Liang Chen ,  Chung-Hau Fei ,  Wen-Chih Yang ,  Jin-Aun Ng ,  Chi Hsin Chang ,  Chun Ming Lin ,  Harry Chuang

IPC: H01L21/00 ,  H01L21/02

CPC classification number: H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.

Abstract translation: 本公开提供一种半导体器件，其包括半导体衬底和形成在衬底中的晶体管。 晶体管包括具有高k电介质和金属栅极的栅极堆叠，形成在栅极叠层的侧壁上的密封层，密封层具有内边缘和外边缘，内边缘与栅叠层的侧壁相接合 ，形成在密封层的外边缘上的隔离物和形成在栅极堆叠的每一侧上的源极/漏极区域，源极/漏极区域包括与外部电极对准的轻掺杂源极/漏极（LDD）区域 密封层的边缘。

公开(公告)号：US20120276732A1

公开(公告)日：2012-11-01

申请号：US13548039

申请日：2012-07-12

Applicant: Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

Inventor： Jian-Hong Lin ,  Kang-Cheng Lin ,  Tzu-Li Lee

IPC: H01L21/768

CPC classification number: H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a semiconductor structure is provided to prevent energy that is used to blow at least one fuse formed on a metal layer above a semiconductor substrate from causing damage on the structure. The semiconductor structure includes a device, guard ring, protection ring, and at least one protection layer. The device is constructed on the semiconductor substrate underneath the fuse. A seal ring, which surrounds the fuse, is constructed on at least one metal layer between the device and the fuse for confining the energy therein. The protection layer is formed within the seal ring, on at least one metal layer between the device and the fuse for shielding the device from being directly exposed to the energy.

Abstract translation: 提供一种用于形成半导体结构的方法，以防止用于吹送形成在半导体衬底上的金属层上的至少一个熔丝的能量引起对结构的损坏。 半导体结构包括器件，保护环，保护环和至少一个保护层。 该器件构造在保险丝下方的半导体衬底上。 围绕熔丝的密封环构造在设备和保险丝之间的至少一个金属层上，以将能量限制在其中。 保护层形成在密封环内，在设备和保险丝之间的至少一个金属层上，用于屏蔽器件不会直接暴露于能量。

公开(公告)号：US20100052077A1

公开(公告)日：2010-03-04

申请号：US12422378

申请日：2009-04-13

Applicant: Peng-Fu Hsu ,  Hsin-Chun Ko ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Peng-Fu Hsu ,  Hsin-Chun Ko ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

Abstract: A high-k metal gate structure including a buffer layer and method of fabrication of such, is provided. The buffer layer may interpose an interface oxide layer and a high-k gate dielectric layer. In one embodiment, the buffer layer includes aluminum oxide. The buffer layer and the high-k gate dielectric layer may be formed in-situ using an atomic layer deposition (ALD) process.

Abstract translation: 提供了包括缓冲层的高k金属栅极结构及其制造方法。 缓冲层可以插入界面氧化物层和高k栅介质层。 在一个实施例中，缓冲层包括氧化铝。 可以使用原子层沉积（ALD）工艺原位形成缓冲层和高k栅介质层。

公开(公告)号：US20100044804A1

公开(公告)日：2010-02-25

申请号：US12427222

申请日：2009-04-21

Applicant: Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

Inventor： Chien-Hao Chen ,  Yong-Tian Hou ,  Kang-Cheng Lin ,  Kuo-Tai Huang

IPC: H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28088 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate, a transistor formed in the substrate, the transistor including a high-k gate dielectric formed over the substrate, the high-k gate dielectric having a first length measured from one sidewall to the other sidewall of the high-k gate dielectric, and a metal gate formed over the high-k gate dielectric, the metal gate having a second length measured from one sidewall to the other sidewall of the metal gate, the second length being smaller than the first length.

Abstract translation: 本公开提供了一种半导体器件，其包括半导体衬底，形成在衬底中的晶体管，晶体管包括形成在衬底上的高k栅极电介质，高k栅极电介质具有从一个侧壁到 高k栅极电介质的另一个侧壁和形成在高k栅极电介质上的金属栅极，金属栅极具有从金属栅极的一个侧壁到另一侧壁测量的第二长度，第二长度小于 第一长。