公开(公告)号：US11854637B2

公开(公告)日：2023-12-26

申请号：US18103603

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Michael R. Spica ,  David G. Springberg

IPC: G11C29/00 ,  G11C29/10 ,  G06F9/30 ,  G06F11/22 ,  G11C29/14

CPC classification number: G11C29/10 ,  G06F9/30101 ,  G06F11/221 ,  G11C29/14

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.

公开(公告)号：US20210026425A1

公开(公告)日：2021-01-28

申请号：US16518267

申请日：2019-07-22

Applicant: Micron Technology, Inc.

Inventor： Michael R. Spica

IPC: G06F1/20 ,  H05K7/20 ,  H05K1/02

Abstract: First event information that is associated with an event that corresponds to a temperature of a memory sub-system is received. Whether the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies a first threshold condition is determined. Responsive to determining that the first event information associated with the event that corresponds to the temperature of the memory sub-system satisfies the first threshold condition, a thermoelectric component (TEC) is caused to change from an inactive state to an active state by decreasing a temperature at a bottom surface of the TEC that is coupled to the memory sub-system as a temperature at a top surface of the TEC increases.

公开(公告)号：US20200243119A1

公开(公告)日：2020-07-30

申请号：US16262111

申请日：2019-01-30

Applicant: Micron Technology, Inc.

Inventor： Michael R. Spica ,  Patrick T. Caraher

IPC: G11C5/14 ,  G06F11/07 ,  G01R19/165

Abstract: A memory sub-system comprises a power management component comprising a plurality of regulators configured to supply respective operating voltages for components of the memory sub-system. The power management component is configured to adjust a regulator voltage level provided to a particular component until an operation state change of the particular component is detected. The power management voltage level is further configured to determine a value of the regulator voltage level at which the operation state change of the particular component is detected.

公开(公告)号：US20230178163A1

公开(公告)日：2023-06-08

申请号：US18103603

申请日：2023-01-31

Applicant: Micron Technology, Inc.

Inventor： Michael R. Spica ,  David G. Springberg

IPC: G11C29/10 ,  G06F9/30 ,  G06F11/22 ,  G11C29/14

CPC classification number: G11C29/10 ,  G06F9/30101 ,  G06F11/221 ,  G11C29/14

Abstract: A system includes a memory device and a processing device coupled to the memory device. The processing device is configured to switch an operating mode of the memory device between a test mode and a non-test mode. The system further includes a test mode access component that is configured to access the memory device while the memory device is in the test mode to perform a test mode operation.

公开(公告)号：US20220230700A1

公开(公告)日：2022-07-21

申请号：US17716972

申请日：2022-04-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/36 ,  G06F9/50 ,  G11C29/22

Abstract: A detection is made by a processing device allocated to a memory device test board of a distributed test platform that a memory sub-system has engaged with a memory device test resource of the memory device test board. A test is identified to be performed for a memory device of the memory sub-system. The test includes first instructions to be executed by a memory sub-system controller of the memory sub-system in performance of the test and second instructions to be executed by the processing device in performance of the test. The second instructions are to cause one or more test condition components of the memory device test resource to generate one or more test conditions to be applied to the memory device while the memory sub-system executes the first instructions. Responsive to a transmission of the first instructions to the memory sub-system controller, the second instructions are executed.

公开(公告)号：US11328789B2

公开(公告)日：2022-05-10

申请号：US16719707

申请日：2019-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/36 ,  G06F9/50 ,  G11C29/22

Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.

公开(公告)号：US20210193250A1

公开(公告)日：2021-06-24

申请号：US16719707

申请日：2019-12-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Gary D. Hamor ,  Michael R. Spica ,  Donald Shepard ,  Patrick Caraher ,  João Elmiro da Rocha Chaves

IPC: G11C29/44 ,  G11C29/56 ,  G11C29/22 ,  G11C29/36 ,  G06F9/50

Abstract: A test rack includes two or more memory device test boards where each memory device test boards includes two or more memory device test resources. Each of the two or more memory device test boards includes a separate processing device allocated to the memory device test resources of a corresponding memory device test boards. A processing device of a test board detects that a first memory sub-system has engaged with a first memory device test resource of the corresponding memory device test board. The processing device identifies a first test to be performed for a first memory device of the first memory sub-system, where the first test includes one or more first test instructions to be executed in performance of the first test. The processing device causes the one or more first test instructions to be transmitted to the first memory sub-system, where the first test is performed by the one or more first test instructions executing at the first memory sub-system.