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公开(公告)号：US20160308547A1
公开(公告)日：2016-10-20
申请号：US15130636
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/1023 , H03M1/0607 , H03M1/68
Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
Abstract translation: 为具有数字偏移量的数模转换器（DAC）提供了系统和方法。 数字偏移可以应用于数模转换器（DAC）的输入端，然后通过DAC将数模转换应用于具有数字偏移量的输入。 数字偏移被设置为考虑与DAC的输入相关的一个或多个条件，其中一个或多个条件影响DAC中的多个转换元件中的一个或多个的开关特性，并且其中每个转换元件处理特定 位到DAC的输入。 数字偏移可以被动态地和自适应地确定，例如基于与输入有关的输入和/或条件。 或者，数字偏移可以是预定的和固定的。 一个或多个调整可以选择性地应用于特定输入条件的数字偏移。
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公开(公告)号：US20150092899A1
公开(公告)日：2015-04-02
申请号：US14563476
申请日：2014-12-08
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
IPC: H04L7/033
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.
Abstract translation: 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。
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公开(公告)号：US20150048960A1
公开(公告)日：2015-02-19
申请号：US14455361
申请日：2014-08-08
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu
Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.
Abstract translation: 为电流转向数模转换器（DAC）中的动态功率开关提供了方法和系统。 DAC电路可以被配置为基于当前转向来应用数模转换，并且特别地包括在转换期间使用动态功率切换。 DAC电路可以包括主部分，其可以将主电源电压连接到主电流源。 主部分可以包括正侧分支和负侧分支，其可以被配置为例如以差分方式转向正侧和负侧电流以实现转换。 动态功率切换可以例如通过将DAC电路中的主电流源连接到次级电源的次级部分来施加。 次级电源电压可以被配置为使得其可以小于用于驱动DAC电路中的电流转向的主电源电压。
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公开(公告)号：US20190115929A1
公开(公告)日：2019-04-18
申请号：US16217348
申请日：2018-12-12
Applicant: Maxlinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
IPC: H03M1/06
CPC classification number: H03M1/0624 , H03M1/66
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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15.发明授权公开(公告)号：US09742421B2
公开(公告)日：2017-08-22
申请号：US15213731
申请日：2016-07-19
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu
CPC classification number: H03M1/08 , H03M1/0617 , H03M1/066 , H03M1/66 , H03M1/74
Abstract: Methods and systems are provided for enhanced digital-to-analog conversions. A segmentation-based digital-to-analog converter (DAC) may be configured for applying digital-to-analog conversions to N-bit inputs. The segmentation-based DAC may comprise a plurality of DAC elements, with each DAC element being operable to apply digital-to-analog conversion based on a single bit, and an encoder operable to generate an x-bit output. The number of DAC elements may be different than number of bits (N) in inputs to the DAC. One or more bits of the N-bit input may be applied to the encoder to generate the x-bit output, with each bit in the x-bit output being applied to a corresponding one of the plurality of DAC elements. Remaining one or more bits of the N-bit input, if any, may be applied directly to a corresponding one or more of the plurality of DAC elements.
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Patent Agency Ranking
公开(公告)号：US09692435B2
公开(公告)日：2017-06-27
申请号：US15130636
申请日：2016-04-15
Applicant: MaxLinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
CPC classification number: H03M1/1023 , H03M1/0607 , H03M1/68
Abstract: Systems and methods are provided for digital-to-analog converter (DAC) with digital offsets. A digital offset may be applied to an input of a digital-to-analog converter (DAC), and digital-to-analog conversions are then applied via the DAC to the input with the digital offset. The digital offset is set to account for one or more conditions relating to inputs to the DAC, with the one or more conditions affect switching characteristics of one or more of a plurality of conversion elements in the DAC, and where each conversion element handles a particular bit in inputs to the DAC. The digital offset may be determined dynamically and adaptively, such as based on the input and/or conditions relating to the input. Alternatively, the digital offset may be pre-determined and fixed. One or more adjustments may be selectively applied to the digital offset for particular input conditions.
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公开(公告)号：US09461666B2
公开(公告)日：2016-10-04
申请号：US14869268
申请日：2015-09-29
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu
IPC: H03M1/66
Abstract: Methods and systems are provided for dynamic power switching in current-steering digital-to-analog converters (DACs). A DAC circuit may be configured to apply digital-to-analog conversions based on current steering, and to particularly incorporate use of dynamic power switching during conversions. The DAC circuit may comprise a main section, which may connect a main supply voltage to a main current source. The main section may comprise a positive-side branch and a negative-side branch, which may be configured to steer positive-side and negative-side currents, such as in a differential manner, to effectuate the conversions. The dynamic power switching may be applied, for example, via a secondary section connecting a main current source in the DAC circuit to a secondary supply voltage. The secondary supply voltage may be configured such that it may be less than the main supply voltage used in driving the current steering in the DAC circuit.
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18.发明授权Localized dynamic element matching and dynamic noise scaling in digital-to-analog converters (DACs) 有权数模转换器（DAC）中的局部动态元件匹配和动态噪声缩放公开(公告)号：US09397678B2
公开(公告)日：2016-07-19
申请号：US14821353
申请日：2015-08-07
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu
CPC classification number: H03M1/08 , H03M1/0617 , H03M1/066 , H03M1/66 , H03M1/74
Abstract: Methods and systems are provided for controlling operations of digital-to-analog converters (DACs), particularly ones comprising multiple DAC elements. In particular, a plurality of DAC elements in a digital-to-analog converter (DAC) may be controlled during digital-to-analog conversions, with the controlling comprising use of a switching arrangement that comprises one or more switching elements configured for controlling switching of each of the plurality of DAC elements. The controlling may comprise forcing one or more of the plurality of DAC elements in the DAC to not switch during the digital-to-analog conversions. Further, the remaining DAC elements may be scrambled. The controlling of the plurality of DAC elements in the DAC may be based on analysis of an input to the DAC that is being converted. The analysis may comprise determining when the input is backed off from full-scale. A switching sequence may be applied, via each of the one or more switching elements.
Abstract translation: 提供了用于控制数模转换器（DAC）的操作的方法和系统，特别是包括多个DAC元件的数模转换器（DAC）的操作。 特别地，在数模转换（DAC）期间可以控制数模转换器（DAC）中的多个DAC元件，其中控制包括使用包括被配置为用于控制开关的一个或多个开关元件的开关装置 的多个DAC元件中的每一个。 控制可以包括迫使DAC中的多个DAC元件中的一个或多个在数模转换期间不被切换。 此外，剩余的DAC元件可能被加扰。 DAC中的多个DAC元件的控制可以基于对正被转换的DAC的输入的分析。 分析可以包括确定输入何时从全尺寸退出。 可以通过一个或多个开关元件中的每一个施加开关序列。
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公开(公告)号：US08934590B2
公开(公告)日：2015-01-13
申请号：US14107212
申请日：2013-12-16
Applicant: MaxLinear, Inc.
Inventor： Jianyu Zhu , Sheng-Yu Peng , Rodney Chandler , Pawan Tiwari , Rahul Bhatia , Eric Fogleman
CPC classification number: H04L7/0334 , H03M1/1215 , H03M1/1245
Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.
Abstract translation: 信号接收器可以包括第一采样电路，其可操作以在特定主采样率下以第一电平进行采样; 第二采样电路，其可操作以以与主采样率相比减小的第二采样率在第二电平中采样第一采样电路的输出; 第三采样电路，其可操作以以与第二采样率相比减小的第三采样率在第三电平，第二采样电路的一个或多个输出中采样; 以及用于将模数转换应用于第三采样电路的一个或多个输出的模数转换（ADC）电路。
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公开(公告)号：US10367515B2
公开(公告)日：2019-07-30
申请号：US16217348
申请日：2018-12-12
Applicant: Maxlinear, Inc.
Inventor： Gaurav Chandra , Tao Zeng , Shantha Murthy Prem Swaroop , Jianyu Zhu
Abstract: A digital-to-analog converter (DAC) controller system may be configured for controlling switching in an associated digital-to-analog converter (DAC), based on a plurality of system inputs that include at least a first system input corresponding to an input applied to the DAC for controlling switching therein, and a second system input that includes a reference control signal. The DAC controller system may include a logic gate circuit that generates a gate output based on two gate inputs that include the first system input and an input set based on the second system input; and a plurality of timing circuits that generate timing outputs for controlling timing of switching in the DAC, which include at least one timing circuit that generates a timing output based on the gate output, with the timing output configured for application in conjunction with and for adjusting a timing output of another timing circuit.
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