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公开(公告)号：US20170041090A1
公开(公告)日：2017-02-09
申请号：US15297595
申请日：2016-10-19
Applicant: MaxLinear, Inc.
Inventor： Glenn Chang , Raja Pullela , Madhukar Reddy , Timothy Gallagher , Shanta Murthy Prem Swaroop , Curtis Ling , Vamsi Paidi , Wenjian Chen
CPC classification number: H04H40/90 , H04N21/6143
Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.
Abstract translation: 直接广播卫星（DBS）接收组件可以包括可以基于由DBS接收组件服务的客户端设备请求的内容在多个配置之间或之间配置的集成电路。 在第一配置中，多个卫星频带可以被集成电路数字化为单个宽带信号。 在第二配置中，卫星频带可以由集成电路数字化为多个单独的窄带信号。 集成电路可以包括多个接收路径，每个接收链包括多个低噪声放大器和多个模数转换器中的相应一个。
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公开(公告)号：US20160080098A1
公开(公告)日：2016-03-17
申请号：US14948436
申请日：2015-11-23
Applicant: MaxLinear, Inc.
Inventor： Glenn Chang , Raja Pullela , Madhukar Reddy , Timothy Gallagher , Shanta Murthy Prem Swaroop , Curtis Ling , Vamsi Paidi , Wenjian Chen
CPC classification number: H04H40/90 , H04N21/6143
Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.
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公开(公告)号：US09203535B2
公开(公告)日：2015-12-01
申请号：US13783130
申请日：2013-03-01
Applicant: MaxLinear, Inc.
Inventor： Glenn Chang , Raja Pullela , Madhukar Reddy , Timothy Gallagher , Shanta Murthy Prem Swaroop , Curtis Ling , Vamsi Paidi , Wenjian Chen
IPC: H04H40/90
CPC classification number: H04H40/90 , H04N21/6143
Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.
Abstract translation: 直接广播卫星（DBS）接收组件可以包括可以基于由DBS接收组件服务的客户端设备请求的内容在多个配置之间或之间配置的集成电路。 在第一配置中，多个卫星频带可以被集成电路数字化为单个宽带信号。 在第二配置中，卫星频带可以由集成电路数字化为多个单独的窄带信号。 集成电路可以包括多个接收路径，每个接收链包括多个低噪声放大器和多个模数转换器中的相应一个。
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公开(公告)号：US10523191B2
公开(公告)日：2019-12-31
申请号：US15651290
申请日：2017-07-17
Applicant: Maxlinear, Inc.
Inventor： Sangeetha Gopalakrishnan , Wenjian Chen , Vamsi Paidi
Abstract: Aspects of methods and systems for high frequency signal selection are provided. The system for high frequency signal selection comprises a first driver and a second driver. The first driver is able to receive a first high frequency input, and the second driver is able to receive a second high frequency input. The output of the first driver is operably coupled, via a first inductive element, to a first resistive load and a first buffer, and the second driver is operably coupled, via a second inductive element, to the output of the first driver. One or both of the first high frequency input and the second high frequency input may be transferred to the first buffer by selectively enabling a current to one or both of the first driver and the second driver, respectively.
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15.发明申请公开(公告)号：US20190280648A1
公开(公告)日：2019-09-12
申请号：US15913127
申请日：2018-03-06
Applicant: Maxlinear, Inc.
Inventor： Wenjian Chen , Sangeetha Gopalakrishnan , Raghava Manas Bachu , Vamsi Paidi
Abstract: Methods and systems for a distributed transmission line multiplexer for a multi-core multi-mode voltage-controlled oscillator (VCO) may comprise a plurality of voltage controlled oscillators (VCOs) arranged adjacent to each other, where each of the plurality of VCOs are operable to generate an output signal at a configurable frequency, an impedance matching circuit comprising a respective driver and impedance matching elements coupled to each of the plurality of VCOs, and an output device coupled to the impedance matching circuit. The impedance matching elements may include capacitors and inductors. Between each adjacent pair of the respective drivers coupled to each of the plurality of VCOs, the impedance matching elements may include two inductors coupled in series between the drivers and a capacitor coupled to ground and to a common node between the two inductors. Impedance values of the capacitors and inductors may be configurable.
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Patent Agency Ranking
公开(公告)号：US10211936B2
公开(公告)日：2019-02-19
申请号：US15907404
申请日：2018-02-28
Applicant: Maxlinear, Inc.
Inventor： Glenn Chang , Raja Pullela , Madhukar Reddy , Timothy Gallagher , Shantha Murthy Prem Swaroop , Curtis Ling , Vamsi Paidi , Wenjian Chen
Abstract: A direct broadcast satellite (DBS) reception assembly may comprise an integrated circuit that is configurable between or among a plurality of configurations based on content requested by client devices served by the DBS reception assembly. In a first configuration, multiple satellite frequency bands may be digitized by the integrated circuit as a single wideband signal. In a second configuration, the satellite frequency bands may be digitized by the integrated circuit as a plurality of separate narrowband signals. The integrated circuit may comprise a plurality of receive paths, each of the receive chains comprising a respective one of a plurality of low noise amplifiers and a plurality of analog-to-digital converters.
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公开(公告)号：US10199998B2
公开(公告)日：2019-02-05
申请号：US15805385
申请日：2017-11-07
Applicant: Maxlinear, Inc.
Inventor： Abhishek Jajoo , Vamsi Paidi
Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
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公开(公告)号：US20170373639A1
公开(公告)日：2017-12-28
申请号：US15699074
申请日：2017-09-08
Applicant: Maxlinear, Inc.
Inventor： Abhishek Jajoo , Pawan Tiwari , Vamsi Paidi
CPC classification number: H03B5/20 , H03B27/00 , H03B2200/009 , H03L7/23
Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals each VCO. The VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs.
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19.发明申请Method And System For A Multi-Core Multi-Mode Voltage-Controlled-Oscillator (VCO) 有权多核多模压控振荡器（VCO）的方法与系统公开(公告)号：US20170033738A1
公开(公告)日：2017-02-02
申请号：US15224530
申请日：2016-07-30
Applicant: Maxlinear, Inc.
Inventor： Abhishek Jajoo , Pawan Tiwari , Vamsi Paidi
CPC classification number: H03B5/20 , H03B27/00 , H03B2200/009 , H03L7/23
Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.
Abstract translation: 用于多核多模式压控振荡器（VCO）的方法和系统可以包括利用在集成电路上对称布置的多个压控振荡器（VCO）产生多个振荡信号，其中VCO的互连可以 被布置在与每对多个VCO等距的位置的安静区域中。 互连环可以在布置的VCO内居中，其包括耦合到所述多个VCO中的每一个的输出端的至少两条导线。 多个VCO可以从互连环中的至少一个导电线路的互连接收控制信号。 多个VCO可以从所述互连环中的导线接收控制信号。 多个VCO中的一对相邻VCO的第一VCO的正端子可以耦合到互连环的相同的导线，作为该对相邻VCO中的第二个的负端子。 互连环是圆形的。 阻抗可将VCO耦合到互连环。 偏置信号可以从互连环传送到多个VCO中的每一个。 多个VCO可以包括从中心点等距离布置的四个VCO。
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公开(公告)号：US20160344398A1
公开(公告)日：2016-11-24
申请号：US15160496
申请日：2016-05-20
Applicant: MaxLinear, Inc.
Inventor： Prasun Kali Bhattacharyya , Prasenjit Bhowmik , Vamsi Paidi
CPC classification number: H03L7/235
Abstract: Systems and methods are provided for cascaded phase-locked loops (PLLs). A plurality of phase-locked loops (PLLs) arranged in a cascaded manner may be used in providing enhanced signal generation. Each PLL generates an output based on a corresponding input and a feedback signal. The input to a first one of plurality of cascaded phase-locked loops (PLLs) comprises an input reference signal; the input to each remaining one of the plurality of the cascaded phase-locked loops (PLLs) corresponds to an output of a preceding one of the plurality of the cascaded phase-locked loops (PLLs); and the output of a last one of the plurality of cascaded phase-locked loops (PLLs) corresponds to an overall output signal of the plurality of cascaded phase-locked loops (PLLs). The frequency of the overall output signal is set based on the one or more adjustments applied in each one of the plurality of cascaded phase-locked loops (PLLs).
Abstract translation: 为级联锁相环（PLL）提供系统和方法。 以级联方式布置的多个锁相环（PLL）可用于提供增强的信号产生。 每个PLL根据相应的输入和反馈信号产生输出。 多个级联锁相环（PLL）中的第一个的输入包括输入参考信号; 对多个级联锁相环（PLL）中的每个剩余的一个的输入对应于多个级联锁相环（PLL）中的前一个的输出; 并且多个级联锁相环（PLL）中的最后一个的输出对应于多个级联锁相环（PLL）的总输出信号。 基于在多个级联锁相环（PLL）中的每一个中施加的一个或多个调整来设置总输出信号的频率。
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