公开(公告)号：US08934590B2

公开(公告)日：2015-01-13

申请号：US14107212

申请日：2013-12-16

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04B1/10 ,  H04L7/033 ,  H03M1/12 ,  H03K9/02

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A signal receiver may comprise a first sampling circuitry that is operable to sample in a first level at a particular main sampling rate; a second sampling circuitry that is operable to sample in a second level, an output of the first sampling circuitry, at a second sampling rate that is reduced compared to the main sampling rate; a third sampling circuitry that is operable to sample in a third level, one or more outputs of the second sampling circuitry, at a third sampling rate that is reduced compared to the second sampling rate; and an analog-to-digital conversion (ADC) circuitry for applying analog-to-digital conversion to one or more outputs of the third sampling circuitry.

Abstract translation: 信号接收器可以包括第一采样电路，其可操作以在特定主采样率下以第一电平进行采样; 第二采样电路，其可操作以以与主采样率相比减小的第二采样率在第二电平中采样第一采样电路的输出; 第三采样电路，其可操作以以与第二采样率相比减小的第三采样率在第三电平，第二采样电路的一个或多个输出中采样; 以及用于将模数转换应用于第三采样电路的一个或多个输出的模数转换（ADC）电路。

公开(公告)号：US10003350B2

公开(公告)日：2018-06-19

申请号：US15617515

申请日：2017-06-08

Applicant: MaxLinear, Inc.

Inventor： Kaveh Moazzami ,  Pawan Tiwari ,  Gaurav Chandra

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46 ,  H03M1/08

CPC classification number: H03M1/1245 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/46 ,  H03M1/468

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

公开(公告)号：US09762181B2

公开(公告)日：2017-09-12

申请号：US15224530

申请日：2016-07-30

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Pawan Tiwari ,  Vamsi Paidi

IPC: H03K3/03 ,  H03B5/20 ,  H03L7/23 ,  H03B27/00

CPC classification number: H03B5/20 ,  H03B27/00 ,  H03B2200/009 ,  H03L7/23

Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

公开(公告)号：US09698811B2

公开(公告)日：2017-07-04

申请号：US15149827

申请日：2016-05-09

Applicant: MaxLinear, Inc.

Inventor： Kaveh Moazzami ,  Pawan Tiwari ,  Gaurav Chandra

IPC: H03M1/00 ,  H03M1/12 ,  H03M1/46 ,  H03M1/08

CPC classification number: H03M1/1245 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/46 ,  H03M1/468

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

公开(公告)号：US20170373639A1

公开(公告)日：2017-12-28

申请号：US15699074

申请日：2017-09-08

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Pawan Tiwari ,  Vamsi Paidi

IPC: H03B5/20 ,  H03B27/00 ,  H03L7/23

CPC classification number: H03B5/20 ,  H03B27/00 ,  H03B2200/009 ,  H03L7/23

Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals each VCO. The VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs.

公开(公告)号：US20170272234A1

公开(公告)日：2017-09-21

申请号：US15419063

申请日：2017-01-30

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04L7/033

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.

公开(公告)号：US20170033738A1

公开(公告)日：2017-02-02

申请号：US15224530

申请日：2016-07-30

Applicant: Maxlinear, Inc.

Inventor： Abhishek Jajoo ,  Pawan Tiwari ,  Vamsi Paidi

IPC: H03B5/20 ,  H03L7/23

CPC classification number: H03B5/20 ,  H03B27/00 ,  H03B2200/009 ,  H03L7/23

Abstract: Methods and systems for a multi-core multi-mode voltage-controlled-oscillator (VCO) may comprise generating a plurality of oscillating signals utilizing a plurality of voltage controlled oscillators (VCOs) arranged symmetrically on an integrated circuit, where interconnects for the VCOs may be arranged in quiet zones at locations equidistant from each pair of the plurality of VCOs. An interconnection ring may be centered within the arranged VCOs that comprises at least two conductive lines that couple to output terminals of each of said plurality of VCOs. The plurality of VCOs may receive control signals from interconnects coupled to at least one conductive line in the interconnection ring. The plurality of VCOs may receive control signals from a conductive line in said interconnection ring. A positive terminal of a first VCO of a pair of adjacent VCOs of the plurality of VCOs may be coupled to a same conductive line of the interconnection ring as a negative terminal of a second of the pair of adjacent VCOs. The interconnection ring ay be circular. Impedances may couple the VCOs to the interconnection ring. Bias signals may be communicated to each of the plurality of VCOs from the interconnection ring. The plurality of VCOs may include four VCOs arranged equidistant from a center point.

Abstract translation: 用于多核多模式压控振荡器（VCO）的方法和系统可以包括利用在集成电路上对称布置的多个压控振荡器（VCO）产生多个振荡信号，其中VCO的互连可以 被布置在与每对多个VCO等距的位置的安静区域中。 互连环可以在布置的VCO内居中，其包括耦合到所述多个VCO中的每一个的输出端的至少两条导线。 多个VCO可以从互连环中的至少一个导电线路的互连接收控制信号。 多个VCO可以从所述互连环中的导线接收控制信号。 多个VCO中的一对相邻VCO的第一VCO的正端子可以耦合到互连环的相同的导线，作为该对相邻VCO中的第二个的负端子。 互连环是圆形的。 阻抗可将VCO耦合到互连环。 偏置信号可以从互连环传送到多个VCO中的每一个。 多个VCO可以包括从中心点等距离布置的四个VCO。

公开(公告)号：US20150092899A1

公开(公告)日：2015-04-02

申请号：US14563476

申请日：2014-12-08

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04L7/033

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A signal receiver may comprise circuitry for applying multi-level sampling to an input signal, using a plurality of sampling rates that comprises at least two different sampling rates, and circuitry for processing one or more outputs of the multi-level sampling. The processing may comprises sampling at a sampling rate that is different than each of the plurality of sampling rates used during the multi-level sampling and applying analog-to-digital conversion. At least one of the sampling rates used during the multi-level sampling and/or the sampling rate used during the processing may be set based on configuring of one or more clock signals used during the multi-level sampling and/or during the processing. At least one of the one or more clock signals may be configured based on reduction of frequency of a corresponding base clock signal.

Abstract translation: 信号接收机可以包括用于使用包括至少两个不同采样速率的多个采样速率以及用于处理多电平采样的一个或多个输出的电路将多电平采样应用于输入信号的电路。 处理可以包括以与在多级采样期间使用的多个采样率中的每一个不同的采样率进行采样并且应用模数转换。 在处理期间使用的多级采样和/或采样率期间使用的采样率中的至少一个可以基于在多级采样期间和/或处理期间使用的一个或多个时钟信号的配置来设置。 可以基于对应的基本时钟信号的频率的降低来配置一个或多个时钟信号中的至少一个。

公开(公告)号：US20180269891A1

公开(公告)日：2018-09-20

申请号：US15983764

申请日：2018-05-18

Applicant: MaxLinear, Inc.

Inventor： Kaveh Moazzami ,  Pawan Tiwari ,  Gaurav Chandra

IPC: H03M1/12 ,  H03M1/46 ,  H03M1/08

CPC classification number: H03M1/1245 ,  H03M1/0836 ,  H03M1/12 ,  H03M1/46 ,  H03M1/468

Abstract: Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.

公开(公告)号：US09985777B2

公开(公告)日：2018-05-29

申请号：US15419063

申请日：2017-01-30

Applicant: MaxLinear, Inc.

Inventor： Jianyu Zhu ,  Sheng-Yu Peng ,  Rodney Chandler ,  Pawan Tiwari ,  Rahul Bhatia ,  Eric Fogleman

IPC: H04L7/033 ,  H04B1/10 ,  H03M1/12

CPC classification number: H04L7/0334 ,  H03M1/1215 ,  H03M1/1245

Abstract: A radio frequency (RF) receiver may comprise a first sampling module that is operable to sample in a first level at a particular main sampling rate; a plurality of second-level sampling modules, wherein each of the plurality of second-level sampling modules is operable to sample in a second level, an output of the first level, at a second sampling rate that is reduced compared to the main sampling rate; and a plurality of third-level modules, each comprising a plurality of third-stage sampling sub-modules that are operable to sample at a third sampling rate that is reduced compared to the second sampling rate, and a plurality of corresponding analog-to-digital conversion (ADC) sub-modules.