公开(公告)号：US12183406B2

公开(公告)日：2024-12-31

申请号：US18238850

申请日：2023-08-28

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Zhenming Zhou ,  Zhenlei Shen ,  Charles See Yeung Kwong

IPC: G11C11/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34

Abstract: It is determined whether a write disturb capability associated with a first location of a memory device satisfies a threshold criterion. Responsive to determining that the write disturb capability associated with the first location of the memory device satisfies the threshold criterion, a plurality of memory units is remapped to a second location of the memory device, wherein a write disturb capability associated with the second location of the memory device does not satisfy the threshold criterion.

公开(公告)号：US20240420784A1

公开(公告)日：2024-12-19

申请号：US18739769

申请日：2024-06-11

Applicant: Micron Technology, Inc.

Inventor： Murong Lang ,  Peng Zhang ,  Lei Lin ,  Zhenming Zhou ,  Jun Wan

IPC: G11C16/34 ,  G11C16/10

Abstract: Aspects of the present disclosure configure a memory sub-system controller to selectively adjust a program pulse for different word line groups of a memory sub-system. The controller receives a request to program data to an individual memory component of a set of memory components. The controller determines that a program erase count (PEC) associated with the individual memory component transgresses a threshold value. The controller, in response to determining that the PEC associated with the individual memory component transgresses the threshold value, selectively adjusts a predetermined program voltage (Vpgm) associated with a subset of word lines (WLs) of the individual memory component based on whether the subset of WLs is associated with an individual WL group (WLG). The controller programs the data to the individual memory component according to the selectively adjusted predetermined Vpgm.

公开(公告)号：US12165709B2

公开(公告)日：2024-12-10

申请号：US17876346

申请日：2022-07-28

Applicant: Micron Technology, Inc.

Inventor： Tingjun Xie ,  Murong Lang ,  Fangfang Zhu ,  Jiangli Zhu ,  Zhenming Zhou

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32

Abstract: A method includes performing, over a time period, a quantity of write operations associated with a quad-level cell (QLC) memory block, determining the time period exceeds a threshold time, designating the QLC memory block as a bimodal, determining a voltage threshold level of a last successful read operation associated with the QLC memory block, and setting a read threshold level of at least a portion of the QLC memory block at the voltage threshold level of the last successful read operation.

公开(公告)号：US20240386972A1

公开(公告)日：2024-11-21

申请号：US18787787

申请日：2024-07-29

Applicant: Micron Technology, Inc.

Inventor： Zhenming Zhou ,  Murong Lang ,  Li-Te Chang

IPC: G11C16/34 ,  G11C11/406

Abstract: An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

公开(公告)号：US20240371450A1

公开(公告)日：2024-11-07

申请号：US18637412

申请日：2024-04-16

Applicant: Micron Technology, Inc.

Inventor： Peng Zhang ,  Lei Lin ,  Zhengang Chen ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

Abstract: A system including a memory device and an operatively coupled processing device to perform operations including: responsive to detecting a power-up event, performing a first read strobe on a first set of a plurality of memory cells addressable by a first wordline, determining a value of a conductivity metric reflecting conductive states of one or more bitlines connected to the first set of the plurality of memory cells, determining, based on the value of the conductivity metric, a read level offset value for a second wordline, wherein the second wordline is adjacent to the first wordline, performing, using the read level offset value, a second read strobe on the second wordline, and responsive to determining that a value of a quality metric produced by the second read strobe satisfies a quality criterion, indicating that a programming operation performed on the second wordline was completed before a power off event.

公开(公告)号：US20240331784A1

公开(公告)日：2024-10-03

申请号：US18619094

申请日：2024-03-27

Applicant: Micron Technology, Inc.

Inventor： Hanping Chen ,  Zhongguang Xu ,  Christina Papagianni ,  Yu-Chung Lien ,  Zhenming Zhou

IPC: G11C16/34 ,  G11C16/10 ,  G11C29/52

CPC classification number: G11C16/3459 ,  G11C16/102 ,  G11C29/52

Abstract: A defective portion of a block of a memory device is identified. The defective portion of the block is programmed with a pre-programming voltage pattern. The pre-programming voltage pattern is programmed to the defective portion of the block before a programming operation is performed on a non-defective portion of the block. A verification operation is caused to be performed on the defective portion of the block.

公开(公告)号：US12073905B2

公开(公告)日：2024-08-27

申请号：US17894528

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation with respect to a set of memory cells connected to a wordline of a memory device; identifying a block family associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; responsive to determining that the value of the data state metric satisfies a threshold criterion, determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

公开(公告)号：US12062394B2

公开(公告)日：2024-08-13

申请号：US17546425

申请日：2021-12-09

Applicant: Micron Technology, Inc.

Inventor： Jian Huang ,  Zhenming Zhou

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C29/4401 ,  G11C2029/1202

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a write operation to program first data to a first set of memory cells addressable by a first wordline of a first plurality of wordlines of a block of the memory device; performing a read operation on a second wordline of the plurality of wordlines, wherein the second wordline is adjacent to the first wordline; determining a number of bits programmed in a first logical level in the second wordline; and responsive to determining that the number of bits set satisfies a threshold criterion, copying second data from the first block to a second block.

公开(公告)号：US12057167B2

公开(公告)日：2024-08-06

申请号：US17897184

申请日：2022-08-28

Applicant: Micron Technology, Inc.

Inventor： Yu-Chung Lien ,  Zhenming Zhou ,  Murong Lang

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10

Abstract: A method includes determining a boundary word line in a partial block of a flash memory device, where the partial block includes blank word lines after the boundary word line; determining a single predefined level of pure data to write in at least one of the blank word lines after the boundary word line; and writing the single predefined level of pure data to at least one of the blank word lines after the boundary word line.

公开(公告)号：US20240233843A1

公开(公告)日：2024-07-11

申请号：US18425383

申请日：2024-01-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Zhongguang Xu ,  Murong Lang ,  Zhenming Zhou

IPC: G11C16/34

CPC classification number: G11C16/3495 ,  G11C16/3404

Abstract: A system includes a memory device having a plurality of memory cells and a processing device operatively coupled to the memory device. The processing device is to determine to perform a rewrite on at least a portion of the plurality of memory cells. The processing device can determine that a number of rewrite operations at first subset of memory cells storing a first logic state fail to satisfy a threshold criterion. The processing device can also cause a rewrite of data stored at a second subset of memory cells storing a second logic state in response to determining the number of rewrite operations performed at the first subset of memory cells fail to satisfy the threshold criterion.