公开(公告)号：US20190296699A1

公开(公告)日：2019-09-26

申请号：US16435321

申请日：2019-06-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H03F3/195 ,  H01L29/417 ,  H01L27/06 ,  H01L29/737 ,  H03F3/213 ,  H01L29/04 ,  H01L29/66 ,  H01L21/285 ,  H01L29/45 ,  H01L21/02 ,  H01L21/768 ,  H01L29/861 ,  H01L21/265 ,  H01L29/06 ,  H01L21/311 ,  H01L21/306 ,  H01L21/027 ,  H01L21/3213 ,  H01L29/207 ,  H01L29/36 ,  H01L23/00 ,  H01L29/423 ,  H01L29/205 ,  H01L29/08 ,  H01L29/10 ,  H03F1/56

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20190190476A1

公开(公告)日：2019-06-20

申请号：US16223297

申请日：2018-12-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Masao KONDO ,  Satoshi TANAKA ,  Yasuhisa YAMAMOTO ,  Takayuki TSUTSUI ,  Isao OBU

IPC: H03G3/30 ,  H03F3/21 ,  H03F1/02 ,  H03F3/195

CPC classification number: H03G3/3042 ,  H03F1/0211 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/222 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/54 ,  H03F2203/21103 ,  H03F2203/21139 ,  H03G2201/106

Abstract: A power amplifier circuit includes a first transistor amplifying a first signal; a second transistor amplifying a second signal; a bias circuit supplying a bias current or voltage to a base or gate of the second transistor; and an attenuator attenuating the first or second signal in accordance with a control voltage supplied from the bias circuit. The attenuator includes a first diode to which the control voltage is supplied, a third transistor including a collector connected to a supply path of the first or second signal, an emitter connected to a ground, and a base to which the control voltage is supplied from the first diode, and a capacitor connected in parallel with the first diode. The control voltage decreases as a second signal power level increases. The third transistor allows part of the first or second signal to pass to the emitter in accordance with the control voltage.

公开(公告)号：US20190172933A1

公开(公告)日：2019-06-06

申请号：US16207084

申请日：2018-11-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Shigeki KOYA ,  Masao KONDO ,  Takayuki TSUTSUI

IPC: H01L29/737 ,  H01L23/00 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L21/02 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66

Abstract: A bipolar transistor including a first collector layer, a second collector layer, a base layer, and an emitter layer is disposed on a substrate. Etching characteristics of the second collector layer are different from etching characteristics of the first collector layer and the base layer. In plan view, an edge of an interface between the first collector layer and the second collector layer is disposed inside an edge of a lower surface of the base layer, and an edge of an upper surface of the second collector layer coincides with the edge of the lower surface of the base layer or is disposed inside the edge of the lower surface of the base layer.

公开(公告)号：US20140167115A1

公开(公告)日：2014-06-19

申请号：US14088510

申请日：2013-11-25

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Atsushi KUROKAWA

IPC: H01L29/73 ,  H01L29/66

CPC classification number: H01L29/7304 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/0658 ,  H01L29/66242 ,  H01L29/7371 ,  H01L2224/48091 ,  H01L2224/49171 ,  H01L2924/1305 ,  H01L2924/19105 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A heterojunction bipolar transistor includes a ballast resistor layer of which resistance increases with an increase in temperature. The ballast resistor layer includes a first ballast resistor sub-layer having a positive temperature coefficient of resistivity in a first temperature range and a second temperature range and a second ballast resistor sub-layer having a negative temperature coefficient of resistivity in the first temperature range and a positive temperature coefficient of resistivity in the second temperature range.

Abstract translation: 异质结双极晶体管包括电阻随温度升高而增加的镇流电阻层。 镇流电阻层包括在第一温度范围内具有正电温度系数和第二温度范围的第一镇流电阻子层和在第一温度范围内具有负电阻率温度系数的第二镇流电阻子层，以及 在第二温度范围内的正电阻率温度系数。

公开(公告)号：US20230395542A1

公开(公告)日：2023-12-07

申请号：US18452668

申请日：2023-08-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuya KOBAYASHI ,  Atsushi KUROKAWA ,  Hiroaki TOKUYA ,  Isao OBU ,  Yuichi SAITO

IPC: H01L23/00 ,  H01L23/31 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L24/05 ,  H01L28/40 ,  H01L23/3171 ,  H01L27/0658 ,  H01L27/0676 ,  H01L2224/05558 ,  H01L28/20 ,  H01L23/3192 ,  H01L27/0664 ,  H01L2224/05573 ,  H01L2224/04105 ,  H01L23/528

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

公开(公告)号：US20210126591A1

公开(公告)日：2021-04-29

申请号：US17143940

申请日：2021-01-07

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA ,  Kenichi NAGURA

IPC: H03F1/52 ,  H01L23/00 ,  H01L29/04 ,  H03F3/213 ,  H01L29/737 ,  H01L27/02 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/06 ,  H01L21/265 ,  H01L29/417 ,  H01L29/423 ,  H01L23/48 ,  H01L29/861 ,  H01L21/768 ,  H03F3/195 ,  H01L21/02 ,  H01L29/36 ,  H01L29/207 ,  H01L29/45 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/027 ,  H01L29/66 ,  H01L21/306 ,  H01L21/311 ,  H03F1/56

Abstract: A circuit element is formed on a substrate made of a compound semiconductor. A bonding pad is disposed on the circuit element so as to at least partially overlap the circuit element. The bonding pad includes a first metal film and a second metal film formed on the first metal film. A metal material of the second metal film has a higher Young's modulus than a metal material of the first metal film.

公开(公告)号：US20200382083A1

公开(公告)日：2020-12-03

申请号：US16995902

申请日：2020-08-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Satoshi TANAKA ,  Takayuki TSUTSUI ,  Yasunari UMEMOTO

IPC: H03F3/21 ,  H03F3/19 ,  H03F1/56 ,  H03F1/02 ,  H01L27/06 ,  H01L21/8252

Abstract: A power amplifier includes initial-stage and output-stage amplifier circuits, and initial-stage and output-stage bias circuits. The initial-stage amplifier circuit includes a first high electron mobility transistor having a source electrically connected to a reference potential, and a gate to which a radio-frequency input signal is inputted, and a first heterojunction bipolar transistor having an emitter electrically connected to a drain of the first high electron mobility transistor, a base electrically connected to the reference potential in an alternate-current fashion, and a collector to which direct-current power is supplied and from which a radio-frequency signal is outputted. The output-stage amplifier circuit includes a second heterojunction bipolar transistor having an emitter electrically connected to the reference potential, a base to which the radio-frequency signal outputted from the first heterojunction bipolar transistor is inputted, and a collector to which direct-current power is supplied and from which a radio-frequency output signal is outputted.

公开(公告)号：US20200373417A1

公开(公告)日：2020-11-26

申请号：US16992067

申请日：2020-08-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Yasunari UMEMOTO ,  Shigeki KOYA ,  Isao OBU

IPC: H01L29/737 ,  H01L29/205 ,  H01L29/10 ,  H01L21/285 ,  H01L21/308 ,  H01L21/306 ,  H01L29/66 ,  H01L29/08

Abstract: A heterojunction bipolar transistor includes a collector layer, a base layer, and an emitter layer that are stacked on a substrate. The collector layer includes a graded semiconductor layer in which an electron affinity increases from a side closer to the base layer toward a side farther from the base layer. An electron affinity of the base layer at an interface closer to the collector layer is equal to an electron affinity of the graded semiconductor layer at an interface closer to the base layer.

公开(公告)号：US20200052663A1

公开(公告)日：2020-02-13

申请号：US16527578

申请日：2019-07-31

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeki KOYA ,  Yasunari UMEMOTO ,  Yuichi SAITO ,  Isao OBU ,  Takayuki TSUTSUI

IPC: H03F3/21 ,  H01L23/498 ,  H01F17/00 ,  H01L23/00 ,  H01L23/552 ,  H03F3/213 ,  H03F1/02 ,  H01L23/66

Abstract: A power amplifier module includes a first substrate and a second substrate, at least part of the second substrate being disposed in a region overlapping the first substrate. The second substrate includes a first amplifier circuit and a second amplifier circuit. The first substrate includes a first transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; a second transformer including a primary winding having a first end and a second end and a secondary winding having a first end and a second end; and multiple first conductors disposed in a row between the first transformer and the second transformer, each of the multiple first conductors extending from the wiring layer on a first main surface to the wiring layer on a second main surface of the substrate.

公开(公告)号：US20200027805A1

公开(公告)日：2020-01-23

申请号：US16588030

申请日：2019-09-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Isao OBU ,  Yasunari UMEMOTO ,  Masahiro SHIBATA

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/00 ,  H01L21/67 ,  H01L21/56 ,  H01L21/52 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48

Abstract: A semiconductor chip includes a single-crystal substrate and a metal electrode on the bottom surface of the substrate. The metal electrode has a region in which a first metal is exposed and a region in which a second metal is exposed, the second metal having a standard electrode potential different from that of the first metal.