公开(公告)号：US20110061905A1

公开(公告)日：2011-03-17

申请号：US12654446

申请日：2009-12-18

Applicant: Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

Inventor： Mi Sun Hwang ,  Jae Joon Lee ,  Myung Sam Kang

IPC: H05K1/03 ,  H05K3/36

CPC classification number: H05K3/10 ,  H05K1/0271 ,  H05K1/09 ,  H05K3/4602 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136

Abstract: There is provided a printed circuit board. The printed circuit board may be configured to include: a core layer in which a bending prevention portion of at least two layers is interposed between a plurality of insulating members and includes metal layers having different thermal expansion coefficients is disposed; a circuit pattern that is formed so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and an insulating layer that is formed on the core layer and includes an opening portion that exposes the circuit pattern, and a method of manufacturing the printed circuit board. According to the above-described printed circuit board and the method of manufacturing the printed circuit board, by disposing a bending prevention portion inside the printed circuit board, a printed circuit board capable of improving the progress rate and the productivity and a method of manufacturing the printed circuit board can be provided.

Abstract translation: 提供了印刷电路板。 印刷电路板可以被构造为包括：芯层，其中至少两层的弯曲防止部分插入在多个绝缘构件之间并且包括具有不同热膨胀系数的金属层; 形成为在芯层的内部和芯层的外表面中的至少一个上具有期望图案的电路图案; 以及形成在芯层上并包括露出电路图案的开口部分的绝缘层，以及制造印刷电路板的方法。 根据上述印刷电路板和印刷电路板的制造方法，通过在印刷电路板内设置弯曲防止部，能够提高进度和生产率的印刷电路板，以及制造印刷电路板的方法 可以提供印刷电路板。

公开(公告)号：US20100193232A1

公开(公告)日：2010-08-05

申请号：US12424511

申请日：2009-04-15

Applicant: Myung Sam Kang ,  Ok Tae Kim ,  Gil Yong Shin ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Ok Tae Kim ,  Gil Yong Shin ,  Kil Yong Yun

IPC: H05K1/11 ,  H05K3/10

CPC classification number: H05K3/4084 ,  H05K3/205 ,  H05K3/328 ,  H05K2201/091 ,  H05K2203/063 ,  H05K2203/1115 ,  H05K2203/1572 ,  Y10T29/49155

Abstract: Disclosed herein are a printed circuit board and a process of manufacturing the printed circuit board. The printed circuit board includes an insulating layer, and circuit layers disposed at both sides of the insulating layer, each of the circuit layers including a land part and a pattern part. The land parts formed on both sides of the insulating layer are coupled to each other using electrical resistance welding. There is no need for a separate interlayer connection structure such as vias or bumps and a process of forming the interlayer connection structure, thus simplifying the printed circuit board and the process.

Abstract translation: 这里公开了印刷电路板和制造印刷电路板的工艺。 印刷电路板包括绝缘层和设置在绝缘层两侧的电路层，每个电路层包括焊盘部分和图案部分。 形成在绝缘层两侧的接地部分使用电阻焊接彼此连接。 不需要诸如通孔或凸块的单独的层间连接结构和形成层间连接结构的过程，因此简化了印刷电路板和工艺。

公开(公告)号：US20090101510A1

公开(公告)日：2009-04-23

申请号：US12314783

申请日：2008-12-16

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: C25D5/02

CPC classification number: H05K3/205 ,  H05K3/421 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2203/0156 ,  H05K2203/0353 ,  H05K2203/0376 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention relates to a high density printed circuit board and a method of manufacturing the same which enable a thin printed circuit board to be manufactured and can overcome problems occurring in a conventional method of manufacturing a printed circuit board because a conventional CCL is not used as a raw material. The high density printed circuit board includes a first insulating layer having a constant thickness, and a pair of first circuit layers embedded in two sides of the first insulating layer, respectively.

Abstract translation: 高密度印刷电路板及其制造方法技术领域本发明涉及能够制造薄印刷电路板的高密度印刷电路板及其制造方法，并且可克服传统的印刷电路板的制造方法中出现的问题，因为不使用传统的CCL 作为原料。 高密度印刷电路板包括具有恒定厚度的第一绝缘层和分别嵌入第一绝缘层两侧的一对第一电路层。

公开(公告)号：US20080212299A1

公开(公告)日：2008-09-04

申请号：US11797084

申请日：2007-04-30

Applicant: Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

Inventor： Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

IPC: H05K1/18 ,  H01R43/00

CPC classification number: H05K1/162 ,  H05K3/205 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09672 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Disclosed are a printed circuit board for improving the tolerance of embedded capacitors and a method of manufacturing the same. The printed circuit board having embedded capacitors is manufactured by transferring and embedding a circuit layer having a lower electrode formed through an additive process into a resin insulating layer, and thereby is minimized in the circuit tolerance conventionally caused by an etching process to thus be applied to capacitors for RF matching.

Abstract translation: 公开了一种用于提高嵌入式电容器的容限的印刷电路板及其制造方法。 具有嵌入式电容器的印刷电路板通过将具有通过添加工艺形成的下电极的电路层转移并嵌入到树脂绝缘层中而被制造，从而在通常由蚀刻工艺引起的电路公差中被最小化，从而被应用于 电容器用于RF匹配。

公开(公告)号：US08546943B2

公开(公告)日：2013-10-01

申请号：US12923037

申请日：2010-08-30

Applicant: Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

Inventor： Jung Hyun Park ,  Nam Keun Oh ,  Sang Duck Kim ,  Jong Gyu Choi ,  Young Ji Kim ,  Ji Eun Kim ,  Myung Sam Kang

IPC: H01L23/13 ,  H01L23/498

CPC classification number: H01L21/76885 ,  H01L21/02112 ,  H01L23/13 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Provided is a ball grid array substrate, a semiconductor chip package, and a method of manufacturing the same. The ball grid array substrate includes an insulating layer having a first surface providing a mounting region for a semiconductor chip, a second surface opposing the first surface, and an opening connecting the second surface with the mounting region of the semiconductor chip, and a circuit pattern buried in the second surface. Since the ball grid array substrate is manufactured by a method of stacking two insulating layers, existing devices can be used, and the ball grid array substrate can be manufactured as an ultra thin plate. In addition, since the circuit pattern is buried in the insulating layer, a high-density circuit pattern can be formed.

Abstract translation: 提供了一种球栅阵列基板，半导体芯片封装及其制造方法。 球栅阵列基板包括绝缘层，其具有提供半导体芯片的安装区域的第一表面，与第一表面相对的第二表面和连接第二表面与半导体芯片的安装区域的开口，以及电路图案 埋在第二面。 由于球栅阵列基板通过堆叠两个绝缘层的方法制造，因此可以使用现有的装置，并且可以将球栅阵列基板制造为超薄板。 此外，由于电路图案被埋在绝缘层中，因此可以形成高密度电路图案。

公开(公告)号：US08464423B2

公开(公告)日：2013-06-18

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H01R9/00 ,  H01R43/16 ,  H01R43/00 ,  H05K3/00 ,  H05K3/02 ,  H05K3/10

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US08415200B2

公开(公告)日：2013-04-09

申请号：US13007444

申请日：2011-01-14

Applicant: Mi Sun Hwang ,  Keung Jin Sohn ,  Eung Suek Lee ,  Myung Sam Kang

Inventor： Mi Sun Hwang ,  Keung Jin Sohn ,  Eung Suek Lee ,  Myung Sam Kang

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/48 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/81192 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15311 ,  H05K3/06 ,  H05K3/4038 ,  H05K3/4647 ,  H05K2203/0384 ,  H01L2924/00015 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Disclosed herein is a method for manufacturing a semiconductor package which uses a base member 120 in which a first metal layer 113, a barrier layer 115, and a second metal layer 117 are stacked on both surface thereof in sequence based on an adhesive member 111 to simultaneously manufacture two printed circuit boards through a single sheet process, thereby making it possible to improve manufacturing efficiency; electrically connects a semiconductor chip 300 to a printed circuit board through a solder bump 250, thereby making it possible to implement a high-density package substrate; and forms a metal post 140 instead of a through hole to required in an interlayer circuit connection, thereby making it possible to reduce costs required in the processing/plating of the through hole.

Abstract translation: 本发明公开了一种半导体封装件的制造方法，该半导体封装件使用基片120，其中第一金属层113，阻挡层115和第二金属层117依次以两个表面层叠在第一金属层113，阻挡层115和第二金属层117上， 同时通过单片工艺制造两个印刷电路板，从而可以提高制造效率; 通过焊料凸块250将半导体芯片300电连接到印刷电路板，从而可以实现高密度封装基板; 并且形成金属柱140而不是层间电路连接所需的通孔，从而可以降低通孔的加工/电镀所需的成本。

公开(公告)号：US20120060365A1

公开(公告)日：2012-03-15

申请号：US13373387

申请日：2011-11-14

Applicant: Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

Inventor： Myung Sam Kang ,  Jeong Woo Park ,  Ok Tae Kim ,  Kil Yong Yun

IPC: H05K3/00

CPC classification number: H05K1/111 ,  H05K1/09 ,  H05K1/115 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0323 ,  H05K2203/0376 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: A method of manufacturing a printed circuit board having a metal bump, including: forming a recess for creation of the metal bump on a first carrier, forming a first barrier layer on the first carrier, and forming an upper circuit layer on the first barrier layer, the upper circuit layer including a metal bump charged in the recess and a circuit pattern; forming a second barrier layer on a second carrier, and forming a lower circuit layer on the second barrier layer; preparing an insulating layer, and transferring the upper and lower circuit layers to the insulating layer; removing the first and second carriers; and removing the first and second barrier layers.

Abstract translation: 一种制造具有金属凸块的印刷电路板的方法，包括：在第一载体上形成用于形成金属凸块的凹部，在第一载体上形成第一阻挡层，并在第一阻挡层上形成上电路层 所述上电路层包括充电在所述凹部中的金属凸块和电路图案; 在第二载体上形成第二阻挡层，并在第二阻挡层上形成下电路层; 制备绝缘层，并将上下电路层转移到绝缘层; 移除第一和第二载体; 以及去除所述第一和第二阻挡层。

公开(公告)号：US08022311B2

公开(公告)日：2011-09-20

申请号：US11797084

申请日：2007-04-30

Applicant: Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

Inventor： Tae Eui Kim ,  Byoung Youl Min ,  Myung Sam Kang ,  Je Gwang Yoo

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H05K3/205 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09672 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49165 ,  Y10T29/49169

Abstract: Disclosed are a printed circuit board for improving the tolerance of embedded capacitors and a method of manufacturing the same. The printed circuit board having embedded capacitors is manufactured by transferring and embedding a circuit layer having a lower electrode formed through an additive process into a resin insulating layer, and thereby is minimized in the circuit tolerance conventionally caused by an etching process to thus be applied to capacitors for RF matching.

Abstract translation: 公开了一种用于提高嵌入式电容器的容限的印刷电路板及其制造方法。 具有嵌入式电容器的印刷电路板通过将具有通过添加工艺形成的下电极的电路层转移并嵌入到树脂绝缘层中而被制造，从而在通常由蚀刻工艺引起的电路容差中被最小化，从而被应用于 电容器用于RF匹配。

公开(公告)号：US07707715B2

公开(公告)日：2010-05-04

申请号：US12005610

申请日：2007-12-28

Applicant: Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

Inventor： Shuhichi Okabe ,  Je Gwang Yoo ,  Chang Sup Ryu ,  Myung Sam Kang ,  Jung Hyun Park ,  Ji Hong Jo ,  Jin Yong An ,  Soon Oh Jung

IPC: H05K3/00

CPC classification number: H05K3/205 ,  H05K3/062 ,  H05K3/108 ,  H05K3/462 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2203/0369 ,  H05K2203/061 ,  H05K2203/0733 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Disclosed is a method of fabricating a multilayer printed circuit board, which enables the formation of a micro circuit able to be realized through a semi-additive process using the CTE and rigidity of a metal carrier on a thin substrate which is difficult to convey.

Abstract translation: 公开了一种制造多层印刷电路板的方法，其能够形成能够通过使用CTE的半添加工艺和难以传送的薄基板上的金属载体的刚性来实现的微电路。