公开(公告)号：US08197702B2

公开(公告)日：2012-06-12

申请号：US12508224

申请日：2009-07-23

Applicant: Myung-Sam Kang ,  Jung-Hyun Park ,  Ji-Eun Kim

Inventor： Myung-Sam Kang ,  Jung-Hyun Park ,  Ji-Eun Kim

IPC: C25D5/02 ,  B32B37/00 ,  B32B38/00

CPC classification number: B32B37/02 ,  B32B2457/08 ,  C25D5/022 ,  H05K3/205 ,  H05K3/428 ,  H05K3/4658 ,  H05K2201/0376 ,  H05K2203/0384

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via.

Abstract translation: 公开了印刷电路板的制造方法。 制造具有用于层间连接的通孔的印刷电路板的方法可以包括在载体的一侧上形成电路图案，将载体的一侧压在绝缘体的一侧，去除载体，形成贯穿该载体的孔 通过处理电路图案的一端，并且在孔内形成导电材料以使导电材料对应于通孔。

公开(公告)号：US20100255634A1

公开(公告)日：2010-10-07

申请号：US12801574

申请日：2010-06-15

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/60 ,  H01L21/50

CPC classification number: H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06541 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A manufacturing method of bottom substrate of package. A bottom substrate of a package on package electrically connected to a top substrate by means of a solder ball, including a core board, a solder ball pad formed on a surface of the core board in correspondence with a location of the solder ball, an insulation layer laminated on the core board, a through hole formed by removing a part of the insulation layer such that the solder ball pad is exposed, and a metallic layer filled in the through hole and connected electrically with the solder ball, allows the number of ICs mounted on a bottom substrate to be increased without increasing the size of a solder ball, and allows the size and pitch of the solder balls to be made smaller by controlling the thickness of the insulation layer laminated on the bottom substrate, whereby more signal transmission is possible between a top substrate and a bottom substrate.

Abstract translation: 封装底部基板的制造方法。 封装的封装的底部衬底通过焊球电连接到顶部衬底，所述焊球包括芯板，与所述焊球的位置对应地形成在所述芯板的表面上的焊球焊盘，绝缘体 层叠在芯板上的通孔，通过去除绝缘层的一部分使得焊球焊盘露出而形成的通孔以及填充在通孔中并与焊球电连接的金属层允许IC的数量 安装在底部基板上以增加焊球的尺寸，并且通过控制层叠在底部基板上的绝缘层的厚度，可以使焊球的尺寸和间距变小，由此更多的信号传输是 可能在顶部基板和底部基板之间。

公开(公告)号：US07802358B2

公开(公告)日：2010-09-28

申请号：US12453832

申请日：2009-05-22

Applicant: Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

Inventor： Hoe-Ku Jung ,  Myung-Sam Kang ,  Jung-Hyun Park

IPC: H05K3/00

CPC classification number: H05K3/4691 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K1/183 ,  H05K1/189 ,  H05K3/4623 ,  H05K2201/055 ,  H05K2201/09536 ,  H05K2201/10515 ,  H05K2203/049 ,  H05K2203/063 ,  Y10T29/49124 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A manufacturing method for rigid-flexible multi-layer printed circuit board including: a flexible substrate of which circuits are formed on both sides and which is bendable; a rigid substrate which is laminated on the flexible substrate and circuits are formed on both sides and a cavity within which a semiconductor chip is mounted is formed; and a bonding sheet adhering the flexible substrate and the rigid substrate and having a insulating property. When the same numbers of the semiconductor chips are mounted or the POP is embodied, the whole thickness of the package can be lower. Also, two more semiconductor chips can be mounted using the space as the thickness of the core layer, and the structure impossible when the number of semiconductor chip mounted on the bottom substrate becomes two from one in conventional technology can be embodied.

Abstract translation: 一种刚性柔性多层印刷电路板的制造方法，包括：柔性基板，其两侧形成有可弯曲的电路; 层叠在柔性基板上的刚性基板和电路形成在两侧，并且形成有安装半导体芯片的空腔; 以及粘合柔性基板和刚性基板并具有绝缘性的粘合片。 当安装相同数量的半导体芯片或实施POP时，封装的整体厚度可以更低。 此外，可以使用空间作为芯层的厚度来安装另外两个半导体芯片，并且可以实现当传统技术中安装在底部基板上的半导体芯片的数量变为二倍时的结构是不可能的。

公开(公告)号：US20090324992A1

公开(公告)日：2009-12-31

申请号：US12320011

申请日：2009-01-14

Applicant: Myung-Sam Kang

Inventor： Myung-Sam Kang

IPC: B32B15/04 ,  C25D5/10 ,  C25D5/12 ,  B32B37/10 ,  B32B37/06

CPC classification number: H05K3/0035 ,  B32B15/14 ,  B32B15/20 ,  B32B2038/0076 ,  B32B2250/40 ,  B32B2255/06 ,  B32B2255/205 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2305/076 ,  B32B2311/00 ,  B32B2457/00 ,  B32B2535/00 ,  C25D5/12 ,  C25D5/48 ,  H05K3/0038 ,  H05K3/025 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2203/0361 ,  H05K2203/1388 ,  Y10T29/49165 ,  Y10T428/1275 ,  Y10T428/12778

Abstract: A metal clad laminate and a method of manufacturing the metal clad laminate are disclosed. The metal clad laminate can include a barrier layer made of a metallic material, a metal foil formed on one side of the barrier layer and coupled with the barrier layer by plating, and an insulator attached to the metal foil. By utilizing the metal clad laminate, the metal foil can be prevented from being perforated when processing a via hole using laser, so that a VOP structure may be implemented with a higher level of reliability.

Abstract translation: 公开了一种覆金属层压板及其制造方法。 金属覆层压板可以包括由金属材料制成的阻挡层，在阻挡层的一侧上形成的金属箔，并且通过电镀与阻挡层耦合，以及附着在金属箔上的绝缘体。 通过利用金属覆层叠体，可以防止在使用激光加工通孔时能够对金属箔进行穿孔，从而可以以更高的可靠性实现VOP结构。

公开(公告)号：US20080264676A1

公开(公告)日：2008-10-30

申请号：US11976207

申请日：2007-10-22

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Jeong-Woo Park ,  Ji-Eun Kim

IPC: H05K1/00

CPC classification number: H05K1/0265 ,  H05K1/116 ,  H05K3/107 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K2201/0379 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2203/0361

Abstract: A method of manufacturing a circuit board that includes: forming a conductive relievo pattern, including a first plating layer, a first metal layer, and a second plating layer stacked sequentially in correspondence with a first circuit pattern, on a seed layer stacked on a carrier; stacking and pressing together the carrier and an insulator, such that a surface of the carrier having the conductive relievo pattern faces the insulator; transcribing the conductive relievo pattern into the insulator by removing the carrier; forming a conduction pattern, including a third plating layer and a second metal layer stacked sequentially in correspondence with a second circuit pattern, on the surface of the insulator having the conductive relievo pattern transcribed; removing the first plating layer and seed layer; and removing the first and second metal layers, can provide a circuit board that has high-density circuit patterns without an increased amount of insulator.

Abstract translation: 一种电路板的制造方法，其特征在于，包括：在堆叠在载体上的种子层上，形成导电消除图案，所述导电解像图案包括依次与第一电路图案对应地层叠的第一镀层，第一金属层和第二镀层 ; 将载体和绝缘体堆叠并压在一起，使得具有导电缓冲图案的载体的表面面向绝缘体; 通过移除载体将导电释放图案转印到绝缘体中; 在具有转印的导电消除图案的绝缘体的表面上形成包括与第二电路图案顺序堆叠的第三镀层和第二金属层的导电图案; 去除第一镀层和籽晶层; 并且去除第一和第二金属层可以提供具有高密度电路图案而不增加绝缘体量的电路板。

公开(公告)号：US20080251494A1

公开(公告)日：2008-10-16

申请号：US12078058

申请日：2008-03-26

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Jeong-Woo Park ,  Jong-Gyu Choi ,  Ji-Eun Kim ,  Myung-Sam Kang

IPC: H01B13/00 ,  C25D5/34

CPC classification number: C25D7/123 ,  H05K3/0038 ,  H05K3/108 ,  H05K3/205 ,  H05K3/421 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/108

Abstract: A method of manufacturing a circuit board is disclosed. The method may include: forming a relievo pattern, which is in a corresponding relationship with a circuit pattern, on a metal layer that is stacked on a carrier; stacking and pressing the carrier onto an insulation layer with the relievo pattern facing the insulation layer; transcribing the metal layer and the relievo pattern into the insulation layer by removing the carrier; forming a via hole in the insulation layer on which the metal layer is transcribed; and filling the via hole and forming a plating layer over the metal layer by performing plating over the insulation layer on which the metal layer is transcribed. As the relievo pattern may be formed on the metal layer stacked on the carrier, and the relievo pattern may be transcribed into the insulation layer, high-density circuit patterns can be formed.

Abstract translation: 公开了一种制造电路板的方法。 该方法可以包括：在层叠在载体上的金属层上形成与电路图案对应关系的释放图案; 将载体堆叠并压制到绝缘层上，其中减震图案面向绝缘层; 通过移除载体将金属层和释放图案转印到绝缘层中; 在所述绝缘层上形成通孔，所述绝缘层中所述金属层被转录到所述绝缘层上; 并通过在其上转印有金属层的绝缘层上进行电镀来填充通孔并在金属层上形成镀层。 由于可以在堆叠在载体上的金属层上形成缓和图案，并且可以将缓冲图案转录到绝缘层中，可以形成高密度电路图案。

公开(公告)号：US20080241361A1

公开(公告)日：2008-10-02

申请号：US12007368

申请日：2008-01-09

Applicant: Ji-Hong Jo ,  Myung-Sam Kang

Inventor： Ji-Hong Jo ,  Myung-Sam Kang

IPC: H05K3/02

CPC classification number: H05K3/20 ,  H05K1/0393 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2203/0191 ,  H05K2203/0376 ,  H05K2203/1536

Abstract: A printed circuit board manufacturing method is disclosed. The printed circuit manufacturing method, which includes forming an adhesive layer on a carrier, adhesiveness of the adhesive layer being changed according to heat; forming a circuit pattern on a surface of the adhesive layer; compressing the carrier into the insulation layer to allow the circuit pattern to face the insulation layer; and separating the carrier from the insulation layer by supplying heat to allow the adhesive to reach a predetermined temperature, can reduce a cost of a transferring process and improve the reliability of products by minimizing the affect on a metal pattern, by using a material having the adhesiveness changed according to the temperature as an adhesive layer.

Abstract translation: 公开了印刷电路板的制造方法。 印刷电路制造方法，其包括在载体上形成粘合剂层，粘合剂层的粘合性根据热而改变; 在粘合剂层的表面上形成电路图案; 将载体压缩到绝缘层中以允许电路图案面向绝缘层; 并通过供应热量使粘合剂达到预定温度而将载体与绝缘层分离，可以通过使用具有以下特征的材料来降低对金属图案的影响，从而降低了转印过程的成本并提高了产品的可靠性 粘合性根据作为粘合层的温度而变化。

公开(公告)号：US20080115355A1

公开(公告)日：2008-05-22

申请号：US11984209

申请日：2007-11-14

Applicant: Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

Inventor： Jung-Hyun Park ,  Byoung-Youl Min ,  Je-Gwang Yoo ,  Myung-Sam Kang

IPC: H05K3/10 ,  H01K3/10

CPC classification number: H05K3/421 ,  H05K1/115 ,  H05K3/205 ,  H05K2201/0394 ,  H05K2201/09545 ,  H05K2201/09563 ,  H05K2203/0353 ,  H05K2203/0542 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board is disclosed. Using the method, which includes embedding a first circuit pattern and a second circuit pattern in one side and the other side of an insulation substrate, forming a via hole by removing portions of the insulation substrate and the first circuit pattern, and electrically connecting the first circuit pattern and the second circuit pattern by forming a plating layer in the via hole, it is possible to form high-density circuits, as circuitry may be formed in portions that might have been occupied by lands, and more circuitry may be implemented for a given area of insulation substrate, whereby a fine-patterned printed circuit board may be implemented that has a high degree of integration. Also, a printed circuit board can be produced which allows good signal transfers between layers and with which fine circuit patterns can be implemented with inexpensive costs.

Abstract translation: 公开了一种制造印刷电路板的方法。 使用该方法，其包括在绝缘基板的一侧和另一侧嵌入第一电路图案和第二电路图案，通过去除绝缘基板和第一电路图案的部分而形成通孔，并且将第一 电路图案和第二电路图案，通过在通孔中形成镀层，可以形成高密度电路，因为电路可以形成为可能已经被焊盘占据的部分，并且可以实现更多的电路用于 可以实现具有高度集成度的精细图案化印刷电路板。 此外，可以制造印刷电路板，其可以在层之间进行良好的信号传输，并且可以以廉价的成本实现精细的电路图案。

公开(公告)号：US20080009128A1

公开(公告)日：2008-01-10

申请号：US11708339

申请日：2007-02-21

Applicant: Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

Inventor： Shuhichi Okabe ,  Myung-Sam Kang ,  Jung-Hyun Park ,  Hoe-Ku Jung ,  Ji-Eun Kim

IPC: H01L21/44

CPC classification number: H05K3/205 ,  H05K3/4038 ,  H05K3/4617 ,  H05K2203/0733 ,  H05K2203/1572

Abstract: A buried pattern substrate and a manufacturing method thereof are disclosed. A method of manufacturing a buried pattern substrate having a circuit pattern formed on a surface, in which the circuit pattern is connected electrically by a stud bump, includes (a) forming the circuit pattern and the stud bump by depositing a plating layer selectively on a seed layer of a carrier film, where the seed layer is laminated on a surface of the carrier film, (b) laminating and pressing the carrier film on an insulation layer such that the circuit pattern and the stud bump face the insulation layer, and (c) removing the carrier film and the seed layer, allows the circuit interconnection to be realized using a copper (Cu) stud bump, so that a drilling process for interconnection is unnecessary, the degree of freedom for circuit design is improved, a via land is made unnecessary and the size of a via is small, to allow higher density in a circuit.

Abstract translation: 公开了掩埋图案基板及其制造方法。 一种制造埋设图形衬底的方法，其中电路图案形成在电路图形通过柱形凸块电连接的表面上，包括：（a）通过在 晶种层层叠在载体膜的表面上的载体膜的种子层，（b）在绝缘层上层叠压制载体膜，使得电路图案和柱状凸块面向绝缘层，和 c）去除载体膜和种子层，允许使用铜（Cu）柱状凸块实现电路互连，使得不需要用于互连的钻孔工艺，提高了电路设计的自由度，通孔焊盘 不必要，并且通孔的尺寸小，以允许电路中的较高密度。

公开(公告)号：US20070290344A1

公开(公告)日：2007-12-20

申请号：US11783871

申请日：2007-04-12

Applicant: Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

Inventor： Myung-Sam Kang ,  Byoung-Youl Min ,  Joon-Sung Kim ,  Je-Gwang Yoo ,  Jong-Gyu Choi

IPC: H01L23/488 ,  H01L21/44

CPC classification number: H01L23/13 ,  H01L21/4857 ,  H01L23/49822 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H05K1/111 ,  H05K3/0023 ,  H05K3/108 ,  H05K3/205 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0394 ,  H05K2203/1572 ,  Y02P70/611 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a printed circuit board, and in particular, to a printed circuit board for a package of electronic components and manufacturing method thereof. One aspect of present invention provides a manufacturing method of a printed circuit board for an electronic component package, which includes: forming a circuit pattern including bonding pads on one side of a first insulation layer, laminating a second insulation layer onto one side of the first insulation layer, and exposing the bonding pads by removing a part of the first insulation layer and the second insulation layer corresponding to the location in which the bonding pads is formed.

Abstract translation: 印刷电路板技术领域本发明涉及一种印刷电路板，特别涉及一种电子元件封装用印刷电路板及其制造方法。 本发明的一个方面提供了一种用于电子部件封装的印刷电路板的制造方法，其包括：形成包括在第一绝缘层的一侧上的焊盘的电路图案，将第二绝缘层层压到第一绝缘层的一侧上 绝缘层，并且通过去除与形成接合焊盘的位置相对应的第一绝缘层和第二绝缘层的一部分来暴露接合焊盘。