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    SURFACE-NORMAL COUPLER FOR SILICON-ON-INSULATOR PLATFORMS
    11.
    发明申请
    SURFACE-NORMAL COUPLER FOR SILICON-ON-INSULATOR PLATFORMS 有权
    硅绝缘子平台的表面 - 正常耦合器

    公开(公告)号：US20150362673A1

    公开(公告)日：2015-12-17

    申请号：US13955705

    申请日：2013-07-31

    Applicant: Oracle International Corporation

    Inventor： Xuezhe Zheng ,  Ivan Shubin ,  John E. Cunningham ,  Ashok V. Krishnamoorthy

    IPC: G02B6/122 ,  G02B6/136

    CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12176

    Abstract: A photonic integrated circuit (PIC) is described. This PIC includes an inverse facet mirror on a silicon optical waveguide for optical proximity coupling between two silicon-on-insulator (SOI) chips placed face to face. Accurate mirror facets may be fabricated in etch pits using a silicon micro-machining technique, with wet etching of the silicon facet at an angle of 45° when etched through the surface. Moreover, by filling the etch pit with polycrystalline silicon or another filling material that has an index of refraction similar to silicon (such as a silicon-germanium alloy), a reflecting mirror with an accurate angle can be formed at the end of the silicon optical waveguide using: a metal coating, a dielectric coating, thermal oxidation, or selective silicon dry etching removal of one side of the etch pit to define a cavity.

    Abstract translation: 描述了一种光子集成电路（PIC）。 该PIC包括在硅光波导上用于在面对面放置的两个绝缘体上硅（SOI）芯片之间的光学邻近耦合的反面镜。 可以使用硅微加工技术在蚀刻凹坑中制造精确的镜面，在通过<100>表面蚀刻时以45°的角度湿蚀刻硅<110>面。 此外，通过用多晶硅或具有类似于硅（诸如硅 - 锗合金）的折射率的另一填充材料填充蚀刻坑，可以在硅光学端部形成具有精确角度的反射镜 波导，其使用：金属涂层，电介质涂层，热氧化或选择性硅干蚀刻去除蚀刻坑的一侧以限定空腔。

    Reflow-compatible optical I/O assembly adapter
    13.
    发明授权
    Reflow-compatible optical I/O assembly adapter 有权

    公开(公告)号：US10591689B2

    公开(公告)日：2020-03-17

    申请号：US15425887

    申请日：2017-02-06

    Applicant: Oracle International Corporation

    Inventor： Chaoqi Zhang ,  Hiren D. Thacker ,  Ivan Shubin ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy

    IPC: G02B6/42 ,  G02B6/38

    Abstract: The disclosed embodiments provide an apparatus for connecting one or more optical fibers to an optoelectronic system. This apparatus includes a packaged optoelectronic module (POeM) comprising an optical connector, a silicon photonic (SiP) chip, an integrated circuit (IC) chip, at least one laser chip and a package substrate. The apparatus also includes an assembly adapter enclosing the POeM, wherein the assembly adapter includes a mechanical transfer (MT) ferrule cavity, which includes one or more coarse-alignment structures to guide an MT ferrule enclosing at least one optical fiber during assembly of the apparatus. The assembly adapter is comprised of a solder-reflow-compatible material to facilitate bonding the assembly adapter to a circuit board.

    Optical mode converter having multiple regions
    16.
    发明授权
    Optical mode converter having multiple regions 有权
    具有多个区域的光模式转换器

    公开(公告)号：US09575251B1

    公开(公告)日：2017-02-21

    申请号：US14823954

    申请日：2015-08-11

    Applicant: Oracle International Corporation

    Inventor： Jin-Hyoung Lee ,  Ivan Shubin ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy

    IPC: G02B6/12 ,  G02B6/14 ,  G02B6/122

    CPC classification number: G02B6/14 ,  G02B6/1228

    Abstract: A standard-CMOS-process-compatible optical mode converter transitions an optical mode size using a series of adjacent regions having different optical mode sizes. In particular, in a partial-slab-mode region, which is adjacent to an initial rib-optical-waveguide-mode region, a width of a slab portion of the rib-type optical waveguide decreases and a width of a rib portion of the rib-type optical waveguide decreases to a first minimum tip size. Then, in a slab-mode region, which is adjacent to the partial-slab-mode region, the width of the slab portion decreases to a second minimum tip size. In addition, a dielectric layer is disposed over the slab portion, the rib portion and the BOX layer in the partial-slab-mode region, the slab portion and the BOX layer in the slab-mode region, and the BOX layer in a released-mode region that is adjacent to the slab-mode region and that does not include the semiconductor layer.

    Abstract translation: 标准CMOS工艺兼容光学模式转换器使用具有不同光学模式尺寸的一系列相邻区域来转换光学模式尺寸。 特别地，在与初始肋 - 光波导模式区域相邻的局部平板模式区域中，肋型光波导的板坯部分的宽度减小，并且肋部分的肋部分的宽度 肋型光波导减小到第一最小尖端尺寸。 然后，在与部分板坯模式区域相邻的板坯模式区域中，板坯部分的宽度减小到第二最小端部尺寸。 此外，介电层设置在部分平板模式区域中的板坯部分，肋部分和BOX层上，板模块区域中的板坯部分和BOX层，以及释放的BOX层 模式区域，其与slab模式区域相邻并且不包括半导体层。

    BACK-SIDE ETCHING AND CLEAVING OF SUBSTRATES
    17.
    发明申请
    BACK-SIDE ETCHING AND CLEAVING OF SUBSTRATES 审中-公开

    公开(公告)号：US20160334577A1

    公开(公告)日：2016-11-17

    申请号：US15223509

    申请日：2016-07-29

    Applicant: Oracle International Corporation

    Inventor： Jin-Hyoung Lee ,  Ivan Shubin ,  Xuezhe Zheng ,  Ashok V. Krishnamoorthy

    IPC: G02B6/13 ,  G02B6/136 ,  G02B6/122 ,  H01L21/78 ,  H01L21/3065

    CPC classification number: G02B6/13 ,  G02B6/122 ,  G02B6/136 ,  H01L21/3065 ,  H01L21/7806

    Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

    BACK-SIDE ETCHING AND CLEAVING OF SUBSTRATES
    20.
    发明申请
    BACK-SIDE ETCHING AND CLEAVING OF SUBSTRATES 有权
    基板的背面蚀刻和清洗

    公开(公告)号：US20150071585A1

    公开(公告)日：2015-03-12

    申请号：US14024227

    申请日：2013-09-11

    Applicant: Oracle International Corporation

    Inventor： Jin Hyoung Lee ,  Ivan Shubin ,  Xuezhe Zheng, II ,  Ashok V. Krishnamoorthy

    IPC: G02B6/122 ,  H01L21/78 ,  G02B6/132

    CPC classification number: G02B6/13 ,  G02B6/122 ,  G02B6/136 ,  H01L21/3065 ,  H01L21/7806

    Abstract: A fabrication technique for cleaving a substrate in an integrated circuit is described. During this fabrication technique, a trench is defined on a back side of a substrate. For example, the trench may be defined using photoresist and/or a mask pattern on the back side of the substrate. The trench may extend from the back side to a depth less than a thickness of the substrate. Moreover, a buried-oxide layer and a semiconductor layer may be disposed on a front side of the substrate. In particular, the substrate may be included in a silicon-on-insulator technology. By applying a force proximate to the trench, the substrate may be cleaved to define a surface, such as an optical facet. This surface may have high optical quality and may extend across the substrate, the buried-oxide layer and the semiconductor layer.

    Abstract translation: 描述了用于在集成电路中切割衬底的制造技术。 在该制造技术期间，沟槽被限定在衬底的背面。 例如，可以使用光致抗蚀剂和/或在衬底的背面上的掩模图案来限定沟槽。 沟槽可以从背侧延伸到小于衬底的厚度的深度。 此外，可以在衬底的前侧上设置掩埋氧化物层和半导体层。 特别地，衬底可以包括在绝缘体上硅技术中。 通过施加靠近沟槽的力，衬底可以被切割以限定诸如光学面的表面。 该表面可以具有高的光学质量并且可以延伸穿过衬底，掩埋氧化物层和半导体层。

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