公开(公告)号：US08898613B2

公开(公告)日：2014-11-25

申请号：US14182821

申请日：2014-02-18

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US08694949B2

公开(公告)日：2014-04-08

申请号：US13748167

申请日：2013-01-23

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US12278198B2

公开(公告)日：2025-04-15

申请号：US17743033

申请日：2022-05-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshikazu Tanaka ,  Tadashi Kameyama ,  Takafumi Betsui

IPC: H01L23/66 ,  H01P3/08

Abstract: A semiconductor device includes a semiconductor package having a differential signal terminal pair, and a wiring board. The wiring board includes a first and a second signal transmission line and a reference potential plane. The first and the second signal transmission line is formed in a first conductive layer and connected to the differential signal terminal pair. The reference potential plane includes a conductive pattern formed in a different conductive layer from the first conductive layer. The conductive pattern includes a first and a second region overlapped with the first and the second signal transmission line in plan view, respectively. The conductive pattern has a plurality of openings in the first and the second region. An area of a first conductive portion of the reference potential plane in the first region becomes equal to an area of a second conductive portion of the reference potential plane in the second region.

公开(公告)号：US11658081B2

公开(公告)日：2023-05-23

申请号：US17326829

申请日：2021-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichi Isozumi ,  Takafumi Betsui ,  Shuuichi Kariyazaki

IPC: H01L21/66 ,  H01L25/065 ,  H01L23/538 ,  H01L23/64

CPC classification number: H01L22/32 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/647 ,  H01L25/0655

Abstract: A semiconductor apparatus includes a mounting board, a system on chip (SOC) package and a memory package which are provided on the mounting board. The SOC package includes a semiconductor chip and a package substrate on which the semiconductor chip is mounted. The semiconductor apparatus further includes a signal wiring line through which a signal between the semiconductor chip and the memory package is transmitted, being provided on the package substrate and in the mounting board and a measurement terminal connected to the signal wiring line on main surface of the package substrate.

公开(公告)号：US10460792B2

公开(公告)日：2019-10-29

申请号：US15975886

申请日：2018-05-10

Applicant: Renesas Electronics Corporation

Inventor： Motoo Suwa ,  Takafumi Betsui

IPC: H01L27/08 ,  G11C11/4076 ,  H01L27/108 ,  H01L23/498 ,  H01L23/538 ,  G11C5/06

Abstract: To provide an electronic device capable of improving a signal quality, the electronic device includes a semiconductor memory device, a semiconductor device configured to access data stored in the semiconductor memory device, and a wiring substrate on which the semiconductor memory device and the semiconductor device are mounted. The wiring substrate includes first and second data wirings electrically connecting the semiconductor device with each first and second data terminal of the semiconductor memory device through first and second wiring layers. The first wiring layer is a wiring layer arranged closer to the semiconductor device than the second wiring layer, and the first data terminal is located farther from the semiconductor device than the second data terminal.

公开(公告)号：US10446531B2

公开(公告)日：2019-10-15

申请号：US15514110

申请日：2014-09-26

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Motoo Suwa

IPC: H01L25/18 ,  H01L21/66 ,  H01L23/00 ,  H01L25/16 ,  H01L25/00 ,  G11C5/02 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/50

Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. A plurality of first semiconductor chips and a second semiconductor chip which controls each of the plurality of first semiconductor chips are mounted side by side on a second wiring substrate of the semiconductor device. Further, the plurality of first semiconductor chips are mounted between a first substrate side of the wiring substrate and an extension line of a first chip side of the second semiconductor chip. Furthermore, the first wiring substrate includes a first power line which supplies a first power potential to each of the plurality of first semiconductor chips and a second power line which supplies a second power potential to the second semiconductor chip and has a width larger than that of the first power line. Also, the second power line intersects the first substrate side of the second wiring substrate and extends from a side of the first substrate side of the second wiring substrate toward the second semiconductor chip when seen in a plan view.

公开(公告)号：US09831209B2

公开(公告)日：2017-11-28

申请号：US15168550

申请日：2016-05-31

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Motoo Suwa

IPC: G06F17/50 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L24/17 ,  H01L23/498 ,  H01L23/49838 ,  H01L23/50 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/1016 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105

Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.

公开(公告)号：US09530457B2

公开(公告)日：2016-12-27

申请号：US14519967

申请日：2014-10-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US09123554B2

公开(公告)日：2015-09-01

申请号：US14037620

申请日：2013-09-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi Kuroda ,  Takafumi Betsui

IPC: H01L23/48 ,  H01L23/52 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/09 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

Abstract: This invention is to improve noise immunity to the power supply and ground of a wiring board and a second semiconductor chip in an interior of a semiconductor device. A first semiconductor chip is mounted over a wiring board, and a second semiconductor chip is mounted in a central part located over the first semiconductor chip. Bottom surface electrodes of power and ground systems in the second semiconductor chip are led to their corresponding external coupling electrodes formed in the central part of the wiring board though chip through vias formed in the central part of the first semiconductor chip. The power and ground system bottom surface electrodes, the through vias and the external coupling electrodes are respectively arranged discretely from each other between the power and ground systems.

Abstract translation: 本发明是为了提高对半导体器件内部的布线板和第二半导体芯片的电源和接地的抗干扰性。 第一半导体芯片安装在布线板上，第二半导体芯片安装在位于第一半导体芯片上方的中心部分。 第二半导体芯片中的电源和接地系统的底表面电极通过形成在第一半导体芯片的中心部分中的通孔的芯片通过形成在布线板的中心部分的对应的外部耦合电极被引导。 电力和地面系统底面电极，通孔和外部耦合电极分别在电源和地面系统之间彼此离散布置。

公开(公告)号：US10153245B2

公开(公告)日：2018-12-11

申请号：US15795365

申请日：2017-10-27

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Motoo Suwa

IPC: H01L23/00 ,  H01L23/498 ,  H01L25/065 ,  H01L23/50

Abstract: Provided is a semiconductor device which can be prevented from increasing in size. The semiconductor device includes a semiconductor chip having a first main surface and a second main surface opposite to the first main surface and a wiring substrate over which the semiconductor chip is mounted such that the second main surface of the semiconductor chip faces a first main surface of the wiring substrate. Over the second main surface of the semiconductor chip, a plurality of first terminals connected with a first circuit and a plurality of second terminals connected with a second circuit are arranged. An arrangement pattern of the plurality of first terminals and an arrangement pattern of the plurality of second terminals include the same arrangement pattern. In a region of the wiring substrate where the first circuit is close to the second circuit when viewed from the first main surface of the semiconductor chip, a voltage line which supplies a power supply voltage to the first circuit is formed. In a region of the wiring substrate where the second circuit is close to the first circuit, a voltage line which supplies the power supply voltage to the second circuit is formed.