公开(公告)号：US10573376B2

公开(公告)日：2020-02-25

申请号：US16271947

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C5/06 ,  G11C11/419 ,  G11C5/14 ,  G11C11/417 ,  G11C11/412

Abstract: A logic circuit in a system LSI (Large Scale Integrated Circuit) is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM (Static Random Access Memory) circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20180144790A1

公开(公告)日：2018-05-24

申请号：US15876132

申请日：2018-01-20

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US09754659B2

公开(公告)日：2017-09-05

申请号：US14940654

申请日：2015-11-13

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/00 ,  G11C11/417 ,  G11C5/14 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US20140219010A1

公开(公告)日：2014-08-07

申请号：US14245124

申请日：2014-04-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/412

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

Abstract translation: 系统LSI中的逻辑电路设置有电源开关，以便在待机时切断开关，从而减少漏电流。 同时，系统LSI的SRAM电路控制衬底偏置以减少漏电流。

公开(公告)号：US20190172528A1

公开(公告)日：2019-06-06

申请号：US16271947

申请日：2019-02-11

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419 ,  G11C11/412 ,  G11C5/14 ,  G11C11/417

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US10020028B2

公开(公告)日：2018-07-10

申请号：US15351600

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US09792959B2

公开(公告)日：2017-10-17

申请号：US15351580

申请日：2016-11-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  G11C5/02 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K3/46

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US10726878B2

公开(公告)日：2020-07-28

申请号：US16010770

申请日：2018-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G11C5/04 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  G11C5/06 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  G11C5/02

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US20170206951A1

公开(公告)日：2017-07-20

申请号：US15478237

申请日：2017-04-03

Applicant: Renesas Electronics Corporation

Inventor： Masanao Yamaoka ,  Koichiro Ishibashi ,  Shigezumi Matsui ,  Kenichi Osada

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/146 ,  G11C5/147 ,  G11C11/4125 ,  G11C11/417 ,  G11C2207/2227

Abstract: A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time, an SRAM circuit of the system LSI controls a substrate bias to reduce leakage current.

公开(公告)号：US08898613B2

公开(公告)日：2014-11-25

申请号：US14182821

申请日：2014-02-18

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F17/50 ,  G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.