公开(公告)号：US20160081186A1

公开(公告)日：2016-03-17

申请号：US14607572

申请日：2015-01-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chun-Hsien Lin ,  Shih-Chao Chiu ,  Yu-Cheng Pai ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/18 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/007 ,  H05K1/0271 ,  H05K3/0026 ,  H05K3/188 ,  H05K3/28 ,  H05K3/4038 ,  H05K3/4682 ,  H05K2203/0152 ,  H05K2203/016 ,  H05K2203/1377

Abstract: The present invention provides a substrate structure and a method of fabricating the substrate substrure. The method includes: forming a first wiring layer on a first carrier, forming a dielectric layer on the first wiring layer, forming a second wiring layer on the dielectric layer, forming an insulating protection layer on the second wiring layer, forming a second carrier on the insulative protection layer, and remvoing the first carrier. The formation of the second carrier provides the substrate structure with adequate rigidity to avoid breakage or warpage such that the miniaturization requirement can be satisfied.

Abstract translation: 本发明提供一种衬底结构和制造衬底基底的方法。 该方法包括：在第一载体上形成第一布线层，在第一布线层上形成电介质层，在介电层上形成第二布线层，在第二布线层上形成绝缘保护层，在第二布线层上形成第二载体 绝缘保护层，并提供第一个载体。 第二载体的形成为基板结构提供足够的刚度以避免断裂或翘曲，从而可以满足小型化要求。

公开(公告)号：US20160079170A1

公开(公告)日：2016-03-17

申请号：US14708249

申请日：2015-05-10

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/538 ,  H01L21/56 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5389 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2224/81

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

Abstract translation: 提供半导体封装结构及其制造方法。 半导体封装结构包括具有相对的第一和第二表面的封装体; 多个第一导电焊盘和形成在封装主体的第一表面上的多个第二导电焊盘; 嵌入在所述封装主体中并电连接到所述第一导电焊盘的半导体部件; 以及嵌入在所述封装主体中的多个导电元件，每个所述导电元件具有电连接到所述第二导电焊盘中的相应一个的第一端和与所述第一端相对并从所述封装体的所述第二表面露出的第二端 。 由于半导体部件嵌入封装主体中，所以半导体封装结构的厚度减小。

公开(公告)号：US20150179598A1

公开(公告)日：2015-06-25

申请号：US14183896

申请日：2014-02-19

Applicant: Siliconware Precision Industries Co., Ltd

Inventor： Shih-Chao Chiu ,  Liang-yi Hung

IPC: H01L23/00 ,  H01L23/28

CPC classification number: H01L24/16 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16058 ,  H01L2224/16237 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01082 ,  H01L2924/014

Abstract: A flip-chip packaging structure is provided, which includes: a packaging substrate having a substrate body and a circuit layer formed on the substrate body, wherein the circuit layer has a plurality of conductive pads embedded in the substrate body and exposed from a surface of the substrate body; and a chip disposed on and electrically connected to the packaging substrate through a plurality of conductive elements, wherein the conductive elements and the exposed portions of the conductive pads have a width ratio in a range of 0.7 to 1.3, thereby improving the product yield and reliability.

Abstract translation: 提供了一种倒装芯片封装结构，其包括：具有基板主体和形成在基板主体上的电路层的封装基板，其中电路层具有嵌入在基板主体中的多个导电焊盘，并从 基体; 以及通过多个导电元件设置在电气连接到封装衬底上的芯片，其中导电元件和导电焊盘的暴露部分的宽度比在0.7至1.3的范围内，从而提高了产品的产量和可靠性 。

公开(公告)号：US10141266B2

公开(公告)日：2018-11-27

申请号：US15621337

申请日：2017-06-13

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Shih-Chao Chiu ,  Chun-Hsien Lin ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package structure and a method of fabricating the same are provided. The semiconductor package structure includes a package body having opposing first and second surfaces; a plurality of first conductive pads and a plurality of second conductive pads formed on the first surface of the package body; a semiconductor component embedded in the package body and electrically connected to the first conductive pads; and a plurality of conductive elements embedded in the package body, each of the conductive elements having a first end electrically connected to a corresponding one of the second conductive pads and a second end opposing the first end and exposed from the second surface of the package body. Since the semiconductor component is embedded in the package body, the thickness of the semiconductor package structure is reduced.

公开(公告)号：US10068842B2

公开(公告)日：2018-09-04

申请号：US15648089

申请日：2017-07-12

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Shih-Chao Chiu ,  Chun-Hsien Lin ,  Yu-Cheng Pai ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

Abstract: A single-layer wiring package substrate and a method of fabricating the same are provided, the method including: forming on a carrier a wiring layer having a first surface and a second surface opposing the first surface and being in contact with the carrier; forming on the carrier and on the wiring layer a dielectric body that has a first side having a first opening, from which a portion of the wiring layer is exposed, and a second side opposing the first side and disposed at the same side as the second surface of the wiring layer; and removing the carrier, with the second side of the dielectric body and the second surface of the wiring layer exposed. Therefore, a coreless package substrate is fabricated, and the overall thickness and cost of the substrate are reduced.

公开(公告)号：US09905438B2

公开(公告)日：2018-02-27

申请号：US15466063

申请日：2017-03-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

公开(公告)号：US20170047240A1

公开(公告)日：2017-02-16

申请号：US15334569

申请日：2016-10-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L21/683 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160021743A1

公开(公告)日：2016-01-21

申请号：US14583317

申请日：2014-12-26

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H05K1/11 ,  H05K3/46 ,  H05K3/40 ,  H05K1/02 ,  H05K3/02

CPC classification number: H01L21/6835 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68381 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H05K3/20 ,  H05K3/4007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/10674

Abstract: A coreless packaging substrate is provided, which includes: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed from the first surface of the dielectric layer, wherein the first circuit layer has a plurality of first conductive pads; a plurality of protruding elements formed on the first conductive pads, respectively, wherein each of the protruding elements has contact surfaces to be encapsulated by an external conductive element; a second circuit layer formed on the second surface of the dielectric layer; and a plurality of conductive vias formed in the dielectric layer for electrically connecting the first circuit layer and the second circuit layer. The present invention strengthens the bonding between the first conductive pads and the conductive elements due to a large contact area between the protruding elements and the conductive elements.

Abstract translation: 提供了一种无芯封装基板，其包括：具有相对的第一和第二表面的电介质层; 所述第一电路层嵌入在所述电介质层中并且从所述电介质层的所述第一表面露出，其中所述第一电路层具有多个第一导电焊盘; 分别形成在第一导电焊盘上的多个突起元件，其中每个突出元件具有被外部导电元件封装的接触表面; 形成在电介质层的第二表面上的第二电路层; 以及形成在电介质层中的多个导电通孔，用于电连接第一电路层和第二电路层。 本发明由于突出元件和导电元件之间的大的接触面积而增强了第一导电焊盘和导电元件之间的接合。

公开(公告)号：US20160013123A1

公开(公告)日：2016-01-14

申请号：US14562972

申请日：2014-12-08

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Yu-Cheng Pai ,  Chun-Hsien Lin ,  Shih-Chao Chiu ,  Wei-Chung Hsiao ,  Ming-Chen Sun ,  Tzu-Chieh Shen ,  Chia-Cheng Chen

IPC: H01L23/498 ,  H05K1/11 ,  H01L25/065 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/13 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/1533 ,  H05K1/111 ,  H05K3/4697 ,  H05K2201/10674

Abstract: A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a dielectric layer on the carrier; forming a plurality of conductive posts in the dielectric layer; and forming a cavity in the dielectric layer to expose the bonding pads, wherein the conductive posts are positioned around a periphery of the cavity, thereby simplifying the fabrication process.

Abstract translation: 提供了一种制造封装结构的方法，其包括以下步骤：提供具有多个焊盘的载体; 在载体上层叠电介质层; 在所述电介质层中形成多个导电柱; 以及在所述电介质层中形成空腔以暴露所述接合焊盘，其中所述导电柱围绕所述空腔的周边定位，由此简化所述制造工艺。

公开(公告)号：US20150348929A1

公开(公告)日：2015-12-03

申请号：US14452731

申请日：2014-08-06

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Wei-Chung Hsiao ,  Chun- Hsien Lin ,  Yu-cheng Pai ,  Ming-Chen Sun ,  Shih-Chao Chiu

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/498 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/1533 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package structure is provided, which includes: a substrate having opposite top and bottom surfaces and a plurality of conductive pads and a plurality of conductive posts formed therein, wherein the conductive pads are exposed from the bottom surface of the substrate, and the conductive posts are electrically connected to the conductive pads and each of the conductive posts has an end surface exposed from the top surface of the substrate; a plurality of first conductive bumps formed on the end surfaces of the conductive posts; a plurality of second conductive bumps formed on the top surface of the substrate, wherein the second conductive bumps are higher than the first conductive bumps; and at least a first electronic element disposed on and electrically connected to the first conductive bumps, thereby increasing the wiring flexibility and facilitating subsequent disposing of electronic elements without changing existing machines.

Abstract translation: 提供了一种封装结构，其包括：具有相对的顶表面和底表面的衬底和形成在其中的多个导电焊盘和多个导电柱，其中，导电焊盘从衬底的底表面露出，导电柱 电连接到导电焊盘，并且每个导电柱具有从衬底的顶表面暴露的端表面; 形成在所述导电柱的端面上的多个第一导电凸块; 形成在所述基板的上表面上的多个第二导电凸块，其中所述第二导电凸块高于所述第一导电凸块; 以及至少第一电子元件，其设置在第一导电凸块上并与之电连接，从而增加布线灵活性，并且便于随后处理电子元件而不改变现有机器。