公开(公告)号：US20210217628A1

公开(公告)日：2021-07-15

申请号：US17219413

申请日：2021-03-31

Applicant: Tokyo Electron Limited

Inventor： Subhadeep KAL ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a workpiece having a surface exposing a target layer composed of silicon and either (1) organic material or (2) both oxygen and nitrogen, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes exposing the surface of the workpiece to a chemical environment containing N, H, and F at a first setpoint temperature to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature to remove the chemically treated surface region of the target layer.

公开(公告)号：US10290553B2

公开(公告)日：2019-05-14

申请号：US15420264

申请日：2017-01-31

Applicant: Tokyo Electron Limited

Inventor： Jacob Theisen ,  Aelan Mosden

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/311 ,  H01L21/67

Abstract: Provided is a method for determining and utilizing process completion of post heat treatment (PHT) of a dry etch process, the method comprising: providing a substrate in a process chamber, the substrate having a film layer and an underlying layer, the film layer having one or more regions; performing a dry etch process to remove the film layer or region of the film layer, the dry etch process generating a byproduct layer; measuring one or more properties of the byproduct layer; adjusting the PHT process based on the measured one or more properties of the byproduct layer; and performing the PHT process to remove the byproduct layer on the substrate; wherein the PHT process utilizes a real time in-situ process to concurrently determine when removal of the byproduct layer is complete.

公开(公告)号：US20180315665A1

公开(公告)日：2018-11-01

申请号：US15965606

申请日：2018-04-27

Applicant: Tokyo Electron Limited

Inventor： Aelan Mosden ,  Cheryl Pereira ,  Subhadeep Kal

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/66

Abstract: Embodiments of the invention provide a method for forming NFET, PFET, or NFET and PFET nanowire devices on a substrate. According to one embodiment, the method includes providing a film stack containing a Si layer, a SiGe layer, and a Ge layer positioned between the Si layer and the SiGe layer, and selectively removing the Ge layer by etching that is selective to the Si layer and the SiGe layer, thereby forming an opening between the Si layer and the SiGe layer. According to another embodiment, the method providing a film stack containing alternating Si and Ge layers, and selectively removing the Ge layers by etching that is selective to the Si layers. According to another embodiment, the method includes providing a film stack containing a plurality of alternating SiGe and Ge layers, and selectively removing the plurality of Ge layers by etching that is selective to the SiGe layers.

公开(公告)号：US11837467B2

公开(公告)日：2023-12-05

申请号：US17862820

申请日：2022-07-12

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Christopher Catano ,  Aelan Mosden

IPC: H01L21/02 ,  H01J37/32 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213

CPC classification number: H01L21/02381 ,  H01J37/32449 ,  H01L21/0234 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01J2237/3341

Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.

公开(公告)号：US20230317465A1

公开(公告)日：2023-10-05

申请号：US17713723

申请日：2022-04-05

Applicant: Tokyo Electron Limited

Inventor： Hamed Hajibabaeinajafabadi ,  Pingshan Luan ,  Aelan Mosden ,  Sergey Voronin

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/31116 ,  H01L29/66439 ,  H01L29/66742 ,  H01L21/02532

Abstract: A method of processing a substrate that includes: positioning a substrate in a plasma processing chamber, the substrate including a layer stack of alternating layers of silicon (Si) layers and silicon-germanium (SiGe) layers, the substrate including a recess that exposes sidewalls of the Si layers and sidewalls of the SiGe layers; flowing a first process gas into the plasma processing chamber; while flowing the first process gas, pulsing a second process gas into the plasma processing chamber at a pulsing frequency; while flowing the first process gas and pulsing the second process gas, applying power to a source electrode and a bias electrode of the plasma processing chamber to generate a plasma in the plasma processing chamber; and exposing the substrate to the plasma to laterally etch a portion of the Si layers selectively to the SiGe layers and form indents between the SiGe layers.

公开(公告)号：US20220238309A1

公开(公告)日：2022-07-28

申请号：US17155772

申请日：2021-01-22

Applicant: Tokyo Electron Limited

Inventor： Pingshan Luan ,  Christopher Catano ,  Aelan Mosden

IPC: H01J37/32 ,  H01L21/311 ,  H01L21/02

Abstract: In certain embodiments, a method of processing a semiconductor substrate includes positioning a semiconductor substrate in a plasma chamber of a plasma tool. The semiconductor substrate includes a film stack that includes silicon layers and germanium-containing layers in an alternating stacked arrangement, with at least two silicon layers and at least two germanium-containing layers. The method includes exposing, in a first plasma step executed in the plasma chamber, the film stack to a first plasma. The first plasma is generated from first gases that include nitrogen gas, hydrogen gas, and fluorine gas. The method includes exposing, in a second plasma step executed in the plasma chamber, the film stack to a second plasma. The second plasma is generated from second gases comprising fluorine gas and oxygen gas. The second plasma selectively etches the silicon layers.

公开(公告)号：US20210020454A1

公开(公告)日：2021-01-21

申请号：US16890141

申请日：2020-06-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Daisuke Ito ,  Matthew Flaugh ,  Yusuke Muraki ,  Aelan Mosden

IPC: H01L21/3213 ,  C23F1/02 ,  C23F1/12

Abstract: A method for the dry removal of a material on a microelectronic workpiece is described. The method includes receiving a substrate having a working surface exposing a metal layer and having at least one other material exposed or underneath the metal layer; and differentially etching the metal layer relative to the other material by exposing the substrate to a controlled gas-phase environment containing an anhydrous halogen compound.

公开(公告)号：US10580660B2

公开(公告)日：2020-03-03

申请号：US15191963

申请日：2016-06-24

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Nihar Mohanty ,  Angelique D. Raley ,  Aelan Mosden ,  Scott W. Lefevre

IPC: H01L21/311 ,  H01L21/67

Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.

公开(公告)号：US09984890B2

公开(公告)日：2018-05-29

申请号：US15448334

申请日：2017-03-02

Applicant: Tokyo Electron Limited

Inventor： Subhadeep Kal ,  Kandabara N. Tapily ,  Aelan Mosden

IPC: H01L21/3065 ,  H01L21/322 ,  H01L21/306 ,  H01J37/32 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L21/3065 ,  H01J37/32357 ,  H01J37/32724 ,  H01L21/0234 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/32135 ,  H01L21/322 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: Isotropic silicon and silicon-germanium etching with tunable selectivity is described. The method includes receiving a substrate having a layer of silicon and a layer of silicon-germanium with sidewall surfaces of silicon and silicon-germanium being uncovered, positioning the substrate in a processing chamber configured for etching substrates, and modifying uncovered surfaces of silicon and silicon-germanium by exposing the uncovered surfaces of silicon and silicon-germanium to radical species. The method further includes executing a gaseous chemical oxide removal process that includes flowing a mixture of a nitrogen-containing gas and a fluorine-containing gas at a first substrate temperature to form a fluorine byproduct followed by executing a sublimation process to remove the fluorine byproduct at a second substrate temperature that is higher than the first substrate temperature, and controlling the second substrate temperature to tune the sublimation rate and etch selectivity of a silicon oxide material relative to a silicon-germanium oxide material.

公开(公告)号：US20170221781A1

公开(公告)日：2017-08-03

申请号：US15420264

申请日：2017-01-31

Applicant: Tokyo Electron Limited

Inventor： Jacob Theisen ,  Aelan Mosden

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/3065 ,  H01L21/311

CPC classification number: H01L22/26 ,  H01L21/31116 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/67253 ,  H01L22/12

Abstract: Provided is a method for determining and utilizing process completion of PHT (PHT) of a dry etch process, the method comprising: providing a substrate in a process chamber, the substrate having a film layer and an underlying layer, the film layer having one or more regions; performing a dry etch process to remove the film layer or region of the film layer, the dry etch process generating a byproduct layer; and measuring one or more properties of the byproduct layer; adjusting the PHT process based on the measured one or more properties of the byproduct layer; performing the PHT process to remove the byproduct layer on the substrate; wherein the PHT process utilizes a real time in-situ process to concurrently determine when removal of the byproduct layer is complete.