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    METHOD OF LINE CUT BY MULTI-COLOR PATTERNING TECHNIQUE
    12.
    发明申请
    METHOD OF LINE CUT BY MULTI-COLOR PATTERNING TECHNIQUE 审中-公开

    公开(公告)号：US20190244826A1

    公开(公告)日：2019-08-08

    申请号：US16269252

    申请日：2019-02-06

    Applicant: Tokyo Electron Limited

    Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

    IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/67

    Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.

    PARTIAL ETCH MEMORIZATION VIA FLASH ADDITION
    17.
    发明申请
    PARTIAL ETCH MEMORIZATION VIA FLASH ADDITION 有权
    部分记忆通过闪存添加

    公开(公告)号：US20160293435A1

    公开(公告)日：2016-10-06

    申请号：US15085186

    申请日：2016-03-30

    Applicant: Tokyo Electron Limited

    Inventor： Elliott Franke ,  Vinayak Rastogi ,  Akiteru Ko ,  Kiyohito Ito

    IPC: H01L21/3065 ,  H01L21/67 ,  H01J37/32 ,  H01L21/308

    CPC classification number: H01L21/30655 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/67069

    Abstract: Provided is a method of creating structure profiles on a substrate using faceting and passivation layers. A first plasma etch process performed generating a faceted sidewall and a desired inflection point; a second plasma etch process is performed using an oxygen, nitrogen, or combined oxygen and nitrogen plasma, generating a passivation layer; and a third plasma etch process using operating variables of an etch chemistry on the faceted sidewall and the passivation layer to induce differential etch rates to achieve a breakthrough on near-horizontal surfaces of the structure, wherein the third plasma etch used is configured to produce a target sidewall profile on the substrate down to the underlying stop layer. Selected two or more plasma etch variables are controlled in the performance of the first plasma etch process, the second plasma etch process, and/or the third plasma etch process in order to achieve target sidewall profile objectives.

    Abstract translation: 提供了使用刻面和钝化层在基底上产生结构轮廓的方法。 执行产生刻面侧壁和期望拐点的第一等离子体蚀刻工艺; 使用氧，氮或组合的氧和氮等离子体进行第二等离子体蚀刻工艺，产生钝化层; 以及使用刻蚀侧壁和钝化层上的蚀刻化学品的操作变量的第三等离子体蚀刻工艺，以诱导差分蚀刻速率以在结构的近水平表面上实现突破，其中所用的第三等离子体蚀刻被配置为产生 基板上的目标侧壁轮廓直到底层停止层。 在第一等离子体蚀刻工艺，第二等离子体蚀刻工艺和/或第三等离子体蚀刻工艺的性能中控制所选择的两个或更多个等离子蚀刻变量，以实现目标侧壁轮廓目标。

    Oblique deposition and etch processes
    18.
    发明授权
    Oblique deposition and etch processes 有权

    公开(公告)号：US12272559B2

    公开(公告)日：2025-04-08

    申请号：US17735800

    申请日：2022-05-03

    Applicant: Tokyo Electron Limited

    Inventor： Akiteru Ko

    IPC: H01L21/308 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3065

    Abstract: A method of processing a substrate that includes receiving a patterned photoresist formed over a substrate, the patterned photoresist defining initial openings, each of the initial openings including a first side and an opposite second side along a first direction; depositing a mask material preferentially on the first side within the initial openings using an oblique deposition process performed at a first angle inclined from the first side; and removing a portion of the patterned photoresist using an oblique etch process performed at a second angle inclined from the second side, the mask material and a remaining portion of the patterned photoresist defining final openings.

    Method and system for capping of cores for self-aligned multiple patterning
    20.
    发明授权
    Method and system for capping of cores for self-aligned multiple patterning 有权

    公开(公告)号：US11651965B2

    公开(公告)日：2023-05-16

    申请号：US16988170

    申请日：2020-08-07

    Applicant: Tokyo Electron Limited

    Inventor： Eric Chih-Fang Liu ,  Akiteru Ko

    IPC: H01L21/033

    CPC classification number: H01L21/0338 ,  H01L21/0335 ,  H01L21/0337

    Abstract: Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

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