中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

125 records (took 0.02 seconds)

    STRUCTURE OF SEMICONDUCTOR DEVICE
    12.
    发明申请
    STRUCTURE OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220093741A1

    公开(公告)日：2022-03-24

    申请号：US17511579

    申请日：2021-10-27

    Applicant: United Microelectronics Corp.

    Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

    IPC: H01L29/10 ,  H01L21/265 ,  H01L29/06 ,  H01L29/167

    Abstract: A structure of semiconductor device is provided, including a substrate. First and second trench isolations are disposed in the substrate. A height of a portion of the substrate is between a top and a bottom of the first and second trench isolations. A gate insulation layer is disposed on the portion of the substrate between the first and second trench isolations. A first germanium (Ge) doped layer region is disposed in the portion of the substrate just under the gate insulation layer. A second Ge doped layer region is in the portion of the substrate, overlapping with the first Ge doped layer region to form a Ge gradient from high to low along a depth direction under the gate insulation layer. A fluorine (F) doped layer region is in the portion of the substrate, lower than and overlapping with the first germanium doped layer region.

    Semiconductor device and manufacturing method thereof
    13.
    发明授权
    Semiconductor device and manufacturing method thereof 有权

    公开(公告)号：US11152515B2

    公开(公告)日：2021-10-19

    申请号：US16572556

    申请日：2019-09-16

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chin-Hung Chen ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Chun-Ya Chiu ,  Chia-Jung Hsu ,  Yu-Hsiang Lin

    IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/306 ,  H01L21/02

    Abstract: A manufacturing method of a semiconductor device includes the following steps. An opening is formed penetrating a dielectric layer on a semiconductor substrate. A stacked structure is formed on the dielectric layer. The stacked structure includes a first semiconductor layer partly formed in the opening and partly formed on the dielectric layer, a sacrificial layer formed on the first semiconductor layer, and a second semiconductor layer formed on the sacrificial layer. A patterning process is performed for forming a fin-shaped structure including the first semiconductor layer, the sacrificial layer, and the second semiconductor layer. An etching process is performed to remove the sacrificial layer in the fin-shaped structure. The first semiconductor layer in the fin-shaped structure is etched to become a first semiconductor wire by the etching process. The second semiconductor layer in the fin-shaped structure is etched to become a second semiconductor wire by the etching process.

    MANUFACTURING METHOD OF EPITAXIAL FIN-SHAPED STRUCTURE
    16.
    发明申请
    MANUFACTURING METHOD OF EPITAXIAL FIN-SHAPED STRUCTURE 审中-公开

    公开(公告)号：US20190295896A1

    公开(公告)日：2019-09-26

    申请号：US15951192

    申请日：2018-04-12

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Po-Kuang Hsieh ,  Kuan-Hao Tseng ,  Yu-Hsiang Lin ,  Shih-Hung Tsai ,  Yu-Ting Tseng

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L21/28 ,  H01L21/321

    Abstract: A manufacturing method of an epitaxial fin-shaped structure includes the following steps. A substrate is provided. A recess is formed in the substrate. An epitaxial layer is formed on the substrate. The epitaxial layer is partly formed in the recess and partly formed outside the recess. The epitaxial layer has a dent formed on the top surface of the epitaxial layer, and the dent is formed corresponding to the recess in a thickness direction of the substrate. A nitride layer is conformally formed on the epitaxial layer. An oxide layer is formed on the nitride layer. A first planarization process is performed to remove a part of the oxide layer, and the first planarization process is stopped on the nitride layer. The epitaxial layer in the recess is patterned for forming at least one epitaxial fin-shaped structure.

    DUMMY CELL ARRANGEMENT AND METHOD OF ARRANGING DUMMY CELLS
    17.
    发明申请
    DUMMY CELL ARRANGEMENT AND METHOD OF ARRANGING DUMMY CELLS 审中-公开

    公开(公告)号：US20190074272A1

    公开(公告)日：2019-03-07

    申请号：US16175867

    申请日：2018-10-31

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chung-Liang Chu ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L27/088

    Abstract: A dummy cell arrangement in a semiconductor device includes a substrate with a dummy region, unit dummy cells arranged in rows and columns in the dummy region, and flexible extended dummy cells arranged in rows and columns filling up remaining dummy region. The unit dummy cell includes exactly one base dummy cell and exactly two fixed dummy cells at opposite sides of the base dummy cell in row direction or in column direction and the flexible extended dummy cell includes at least two base dummy units and a plurality of flexible dummy units at two opposite sides of the two base dummy units in row direction or in column direction. The base dummy cell consists of at least one fin, at least one gate and at least one contact, while the flexible dummy cell consists of one gate and one contact without any fin.

    Semiconductor device and method of fabricating the same
    20.
    发明授权
    Semiconductor device and method of fabricating the same 有权

    公开(公告)号：US12262555B2

    公开(公告)日：2025-03-25

    申请号：US17746964

    申请日：2022-05-18

    Applicant: United Microelectronics Corp.

    Inventor： Jia-He Lin ,  Yu-Ruei Chen ,  Yu-Hsiang Lin

    IPC: H10D64/01 ,  H10D30/01 ,  H10D30/62 ,  H10D62/10

    Abstract: A semiconductor device includes a substrate, a plurality of planar transistors, a fin-type field effect transistor and a first nonactive structure. The substrate includes a first region and a second region. The first region includes a plurality of first planar active regions and a nonactive region. The nonactive region is located between or aside the plurality of first planar active regions and includes a second planar active region. The second region has a fin active region. The plurality of planar transistors are located in the plurality of first planar active regions within the first region. The fin-type field effect transistor is located on the fin active region within the second region. The first nonactive structure is located in the nonactive region between the plurality of planar transistors.

Patent Agency Ranking