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    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE
    14.
    发明申请
    MAGNETIC TUNNEL JUNCTION (MTJ) DEVICE 有权

    公开(公告)号：US20210013395A1

    公开(公告)日：2021-01-14

    申请号：US16529740

    申请日：2019-08-01

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Ting-Hsiang Huang ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L43/02

    Abstract: A magnetic tunnel junction (MTJ) device includes two magnetic tunnel junction elements and a metal interconnection. The two magnetic tunnel junction elements are arranged side by side at a first direction. The metal interconnection is disposed between the magnetic tunnel junction elements, wherein the metal interconnection includes a contact plug part having a long shape at a top view, and the long shape has a length at a second direction larger than a width at the first direction, wherein the second direction is orthogonal to the first direction.

    MEMORY DEVICE
    15.
    发明申请
    MEMORY DEVICE 审中-公开

    公开(公告)号：US20200051922A1

    公开(公告)日：2020-02-13

    申请号：US16059046

    申请日：2018-08-09

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Meng-Jun Wang ,  Jiunn-Hsiung Liao ,  Yu-Tsung Lai

    IPC: H01L23/544 ,  H01L23/528

    Abstract: A memory device includes an insulation layer, an interconnection structure disposed in the insulation layer, a dielectric layer disposed on the insulation layer and the interconnection structure, a connection hole disposed on the interconnection structure and penetrates the dielectric layer, an alignment mark trench penetrating the dielectric layer on a peripheral region, a first patterned conductive layer, and a patterned memory material layer. The first patterned conductive layer includes a connection structure at least partly disposed in the connection hole and a first pattern disposed in the alignment mark trench. The patterned memory material layer includes a first memory material pattern disposed on the connection structure and a second memory material pattern disposed in the alignment mark trench. Manufacturing yield and alignment condition of forming the memory device may be improved by disposing a part of the first patterned conductive layer in the alignment mark trench.

    Method of forming patterned mask layer
    16.
    发明授权
    Method of forming patterned mask layer 有权

    公开(公告)号：US09779942B1

    公开(公告)日：2017-10-03

    申请号：US15220386

    申请日：2016-07-26

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Wei Kuo ,  Yu-Tsung Lai ,  Jiunn-Hsiung Liao

    IPC: H01L21/033 ,  H01L21/311

    CPC classification number: H01L21/0337 ,  H01L21/31144

    Abstract: A method of forming a patterned mask layer includes the following steps. A plurality of support features is formed on a mask layer. A plurality of spacers is formed on side walls of the support features. A patterned protection layer is formed on the support features and top surfaces of the spacers. At least a part of side surfaces of the spacers are not covered by the patterned protection layer, and the patterned protection layer is formed in a process environment containing methane (CH4). A trimming process is then performed to remove a part of each of the spacers. Tapered parts of the spacers may be removed by the trimming process before the step of etching the mask layer with the spacers as a mask, and the critical dimension uniformity of the patterned mask layer may be improved accordingly.

    Manufacturing method for forming a self aligned contact
    17.
    发明授权
    Manufacturing method for forming a self aligned contact 有权
    用于形成自对准接触的制造方法

    公开(公告)号：US08993433B2

    公开(公告)日：2015-03-31

    申请号：US13902977

    申请日：2013-05-27

    Applicant: United Microelectronics Corp.

    Inventor： Chieh-Te Chen ,  Yu-Tsung Lai ,  Hsuan-Hsu Chen ,  Feng-Yi Chang ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/4763 ,  H01L21/44 ,  H01L21/768

    CPC classification number: H01L21/76816 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485

    Abstract: The present invention provides a manufacturing method of a semiconductor device, at least containing the following steps: first, a substrate is provided, wherein a first dielectric layer is formed on the substrate, at least one metal gate is formed in the first dielectric layer and at least one source drain region (S/D region) is disposed on two sides of the metal gate, at least one first trench is then formed in the first dielectric layer, exposing parts of the S/D region. The manufacturing method for forming the first trench further includes performing a first photolithography process through a first photomask and performing a second photolithography process through a second photomask, and at least one second trench is formed in the first dielectric layer, exposing parts of the metal gate, and finally, a conductive layer is filled in each first trench and each second trench.

    Abstract translation: 本发明提供一种半导体器件的制造方法，至少包括以下步骤：首先，提供基板，其中在基板上形成第一介电层，在第一介电层中形成至少一个金属栅极， 至少一个源极漏极区域（S / D区域）设置在金属栅极的两侧，然后在第一介电层中形成至少一个第一沟槽，暴露S / D区域的部分。 用于形成第一沟槽的制造方法还包括通过第一光掩模执行第一光刻工艺并通过第二光掩模执行第二光刻工艺，并且在第一电介质层中形成至少一个第二沟槽，暴露部分金属栅极 并且最后，在每个第一沟槽和每个第二沟槽中填充导电层。

    Method for Forming Semiconductor Structure Having Opening
    18.
    发明申请
    Method for Forming Semiconductor Structure Having Opening 审中-公开
    形成具有开口的半导体结构的方法

    公开(公告)号：US20140342553A1

    公开(公告)日：2014-11-20

    申请号：US13893349

    申请日：2013-05-14

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chieh-Te Chen ,  Feng-Yi Chang ,  Hsuan-Hsu Chen ,  Yu-Tsung Lai ,  Chih-Sen Huang ,  Ching-Wen Hung

    IPC: H01L21/768 ,  H01L21/283

    CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76816

    Abstract: According to one embodiment of the present invention, a method for forming a semiconductor structure having an opening is provided. First, a substrate is provided, wherein a first region and a second region are defined on the substrate and an overlapping area of the first region and the second region is defined as a third region. Then, a material layer is formed on the substrate. A first hard mask and a second hard mask are formed on the material layer. The first hard mask in the first region is removed to form a patterned first hard mask. The second hard mask in the third region is removed to form a patterned second hard mask. Lastly, the material layer is patterned by using the patterned second hard mask layer as a mask to form at least an opening in the third region only.

    Abstract translation: 根据本发明的一个实施例，提供一种形成具有开口的半导体结构的方法。 首先，提供衬底，其中在衬底上限定第一区域和第二区域，并且将第一区域和第二区域的重叠区域定义为第三区域。 然后，在基板上形成材料层。 第一硬掩模和第二硬掩模形成在材料层上。 第一区域中的第一硬掩模被去除以形成图案化的第一硬掩模。 去除第三区域中的第二硬掩模以形成图案化的第二硬掩模。 最后，通过使用图案化的第二硬掩模层作为掩模来对材料层进行图案化，以仅在第三区域中形成至少一个开口。

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