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    MEMORY DEVICE AND METHOD FOR FORMING THE SAME
    11.
    发明申请
    MEMORY DEVICE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20210366917A1

    公开(公告)日：2021-11-25

    申请号：US16900511

    申请日：2020-06-12

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Zhongwang SUN ,  Rui SU ,  Zhong ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582

    Abstract: Memory device includes a bottom-select-gate (BSG) structure including cut slits vertically through the BSG structure, on a substrate. A cell-layers structure is formed on the BSG structure. Gate-line slits are formed vertically through the cell-layers structure and the BSG structure, into the substrate and arranged along a first lateral direction to distinguish finger regions. A first gate-line slit is between first and second finger regions and includes gate-line sub-slits. The first finger region is divided into a first string region and a second string region by a first cut-slit, formed in the first finger region along a second lateral direction and further extended into at least the second finger region along the first lateral direction. At least one BSG defined by the first cut-slit is located in at least the second finger region to connect to cell strings in the first string region through an inter-portion between adjacent gate-line sub-slits.

    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY
    12.
    发明申请
    CONTACT STRUCTURES FOR THREE-DIMENSIONAL MEMORY 有权

    公开(公告)号：US20210287991A1

    公开(公告)日：2021-09-16

    申请号：US16875180

    申请日：2020-05-15

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Zhongwang SUN ,  Zhong ZHANG ,  Wenxi ZHOU ,  Lei LIU ,  Zhiliang XIA

    IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/321 ,  H01L21/768

    Abstract: Embodiments of 3D memory structures and methods for forming the same are disclosed. The fabrication method includes disposing an alternating dielectric stack on a substrate, wherein the alternating dielectric stack having first and second dielectric layers alternatingly stacked on top of each other. Next, a plurality of contact openings can be formed in the alternating dielectric stack such that a dielectric layer pair can be exposed inside at least one of the plurality of contact openings. The method further includes forming a film stack of alternating conductive and dielectric layers by replacing the second dielectric layer with a conductive layer, and forming a contact structure to contact the conductive layer in the film stack of alternating conductive and dielectric layers.

    EMBEDDED PAD STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES
    13.
    发明申请
    EMBEDDED PAD STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES 有权

    公开(公告)号：US20210265377A1

    公开(公告)日：2021-08-26

    申请号：US17318730

    申请日：2021-05-12

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Jun CHEN ,  Zhiliang XIA ,  Li Hong XIAO

    IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/11582

    Abstract: Embodiments of 3D memory devices are disclosed. A disclosed 3D memory device can comprises an array interconnect layer disposed over an alternating conductor/dielectric stack and including a first array interconnect structure. Tbe 3D memory device can further comprises a peripheral interconnect layer disposed over a first peripheral device and including a first peripheral interconnect structure. A pad can be embedded in the peripheral interconnect layer and electrically connected with the first peripheral device through the first peripheral interconnect structure. The array interconnect layer is bonded with the peripheral interconnect layer, such that the first array interconnect structure is in electrical contact with the first peripheral interconnect structure.

    3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME
    14.
    发明申请
    3D NAND MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20210265268A1

    公开(公告)日：2021-08-26

    申请号：US17113519

    申请日：2020-12-07

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Rui SU ,  Zhongwang SUN ,  Wenxi ZHOU ,  Zhiliang XIA

    IPC: H01L23/528 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L23/522 ,  H01L21/768

    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a stack of word line layers and insulating layers that are stacked alternatingly over the substrate, and channel structures formed in a first array region and a second array region of the stack. The first array region and the second array region are positioned at opposing sides of the stack. A first staircase is formed in a connection region of the stack over the substrate. The connection region is arranged between the first and second array regions and the first staircase has non-quadrilateral treads. A second staircase is formed in the connection region of the stack over the substrate and the second staircase has non-quadrilateral treads. The connection region in the stack includes a separation region between the first and second staircases.

    THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
    15.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF 审中-公开

    公开(公告)号：US20200273875A1

    公开(公告)日：2020-08-27

    申请号：US16458401

    申请日：2019-07-01

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Zhong ZHANG ,  Wenyu HUA ,  Zhiliang XIA

    IPC: H01L27/11582 ,  H01L21/033

    Abstract: The present disclosure provides a three-dimensional (3D) memory device and a method for forming the same. The 3D memory device can comprise a channel structure region including a plurality of channel structures; a first staircase structure in a first staircase region including a plurality of division block structures arranged along a first direction on a first side of the channel structure, and a second staircase structure in a second staircase region including a plurality of division block structures arranged along the first direction on a second side of the channel structure. A first vertical offset defines a boundary between adjacent division block structures. Each division block structure includes a plurality of staircases arranged along a second direction that is different from the first direction. Each staircase includes a plurality of steps arranged along the first direction.

    MEMORY DEVICE USING COMB-LIKE ROUTING STRUCTURE FOR REDUCED METAL LINE LOADING
    16.
    发明申请
    MEMORY DEVICE USING COMB-LIKE ROUTING STRUCTURE FOR REDUCED METAL LINE LOADING 审中-公开

    公开(公告)号：US20200082886A1

    公开(公告)日：2020-03-12

    申请号：US16168157

    申请日：2018-10-23

    Applicant: Yangtze Memory Technologies Co., Ltd.

    Inventor： Zongliang HUO ,  Li Hong XIAO ,  Zhiliang XIA

    IPC: G11C16/08 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L29/792

    Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefor are disclosed. In an example, the memory device includes a substrate and one or more peripheral devices on the substrate. The memory device also includes one or more interconnect layers and a semiconductor layer disposed over the one or more interconnect layers. A layer stack having alternating conductor and insulator layers is disposed above the semiconductor layer. A plurality of structures extend vertically through the layer stack. A first set of conductive lines are electrically coupled with a first set of the plurality of structures and a second set of conductive lines are electrically coupled with a second set of the plurality of structures different from the first set. The first and second sets of conductive lines are vertically distanced from opposite ends of the plurality of structures.

    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS
    18.
    发明申请
    NON-VOLATILE MEMORY DEVICES AND DATA ERASING METHODS 有权

    公开(公告)号：US20250111880A1

    公开(公告)日：2025-04-03

    申请号：US18977750

    申请日：2024-12-11

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Tao YANG ,  Dongxue ZHAO ,  Lei LIU ,  Kun ZHANG ,  Wenxi ZHOU ,  Zhiliang XIA ,  Zongliang HUO

    IPC: G11C16/16 ,  G11C16/04

    Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

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