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公开(公告)号：US09817972B2
公开(公告)日：2017-11-14
申请号：US15044652
申请日：2016-02-16
Applicant: OBERTHUR TECHNOLOGIES
Inventor： Nicolas Bousquet , Yannick Sierra
Abstract: An electronic assembly for an electronic device may include a detection module to detect a security anomaly of a Rich-OS operating system and a disabling module to disable at least one secure function of the electronic device in response to the detection. The disablement nevertheless allows use of the electronic device in fail-soft mode. The electronic assembly may be implemented such that these two modules are dependent on a trusted operating system, and the trusted operating system and the Rich-OS operating system may be stored in a memory of the electronic assembly and executed on the electronic assembly.
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12.发明授权公开(公告)号：US09804941B1
公开(公告)日：2017-10-31
申请号：US15654228
申请日：2017-07-19
Applicant: Lidong Qu
Inventor： Lidong Qu
Abstract: The present invention relates to a method and system that use data tags to track tasks in applications to provide Object-to-Object (OTO) services. A first application data tag is issued by a data tag server as in an OTO service platform in response to an initiation of a first application by a first initiator. The first data tag specifies at least one first task for fulfilling a first service. The first application data tag is scanned by a first user terminal by a first participant. A first action data tag is issued by the data tag server. A first dynamically variable task data tag is issued by the data tag server to track the first task in the first action. The first dynamically variable task data tag is updated to record the completion of the first task in the first action when the first task is completed.
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13.发明申请公开(公告)号：US20170153985A1
公开(公告)日：2017-06-01
申请号：US15432307
申请日：2017-02-14
Applicant: International Business Machines Corporation
Inventor： Tong CHEN , John Kevin O'BRIEN , Zehra Noman SURA
IPC: G06F12/1027 , G06F12/1009
CPC classification number: G06F12/1027 , G06F8/65 , G06F8/751 , G06F9/4552 , G06F11/073 , G06F11/0772 , G06F11/0793 , G06F11/28 , G06F11/3632 , G06F12/1009 , G06F2212/1024 , G06F2212/65 , G06F2212/68 , G06F2212/684
Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.
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公开(公告)号：US20170031750A1
公开(公告)日：2017-02-02
申请号：US15221409
申请日：2016-07-27
Applicant: Microchip Technology Incorporated
Inventor： Darren Wenn
CPC classification number: G06F11/1004 , G06F9/4843 , G06F11/08 , G06F11/1012 , G06F11/1435 , G06F11/28
Abstract: An integrated circuit includes comprising a cyclic redundancy check (CRC) circuit configured to read data identifying an execution path from code executed by a processor, determine a CRC check value for the data, and, based upon the CRC check value, determine whether the execution is valid.
Abstract translation: 一种集成电路，包括：循环冗余校验（CRC）电路，被配置为从由处理器执行的代码读取识别执行路径的数据，确定数据的CRC校验值，并且基于CRC校验值确定执行 已验证。
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公开(公告)号：US09535784B2
公开(公告)日：2017-01-03
申请号：US14623706
申请日：2015-02-17
Applicant: International Business Machines Corporation
Inventor： Edgar R. Cordero , Timothy J. Dell , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
CPC classification number: G06F11/10 , G06F11/1048 , G06F11/2017 , G06F11/28 , H03M13/29
Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.
Abstract translation: 本发明的示例性实施例公开了一种用于监视第一纠错码（ECC）设备的方法和系统，用于如果第一ECC设备开始失败或失败，则用第二ECC设备故障并替换第一ECC设备。 在一个步骤中，如果超过指定数量的可校正错误或者发生不可校正的错误，则示例性实施例对ECC设备执行环回测试。 在另一步骤中，示例性实施例用通过环回测试的ECC设备替代了对环回测试失败的ECC设备。
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Patent Agency Ranking
公开(公告)号：US20160357464A1
公开(公告)日：2016-12-08
申请号：US15120837
申请日：2014-06-26
Applicant: HITACHI, LTD.
Inventor： Takayuki SUZUKI , Toru TANAKA , Keisuke HATASAKI , Toshio OTANI , Atsumi TERAYAMA
IPC: G06F3/06
Abstract: A management server acquires storage and application information from a first system to store the information. The storage information includes storage area correspondence information indicating a correspondence between a storage area and a processor. The application information includes application correspondence information indicating a correspondence between the processor and an application, and application configuration information indicating a past Input/Output (IO) load on the storage area. The management server estimates an IO load on the storage area by the application based on the storage and application information to obtain an estimated value, and determines whether or not a copy processable period, a period in which a copy process of data can be performed is present, based on the data size and the estimated value. When the copy processable period is present, the management server transmits a copy indication including a start time of the copy processable period to a copy processing server.
Abstract translation: 管理服务器从第一系统获取存储和应用信息以存储信息。 存储信息包括指示存储区域和处理器之间的对应关系的存储区域对应信息。 应用信息包括指示处理器和应用之间的对应关系的应用对应信息以及指示在存储区域上的过去输入/输出（IO）负载的应用配置信息。 管理服务器基于存储和应用信息来估计应用对存储区域的IO负载，以获得估计值，并且确定是否可以执行复制处理周期，可以执行数据的复制处理的周期是 存在，基于数据大小和估计值。 当存在可复制可处理时段时，管理服务器将包括可复制可处理周期的开始时间的复制指示发送到复制处理服务器。
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公开(公告)号：US20160266992A1
公开(公告)日：2016-09-15
申请号：US14998055
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
CPC classification number: G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
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公开(公告)号：US20160203019A1
公开(公告)日：2016-07-14
申请号：US14998047
申请日：2015-12-24
Applicant: Intel Corporation
Inventor： Ravi Rajwar , Bret L. Toll , Konrad K. Lai , Matthew C. Merten , Martin G. Dixon
CPC classification number: G06F11/28 , G06F9/30047 , G06F9/30076 , G06F9/30087 , G06F9/3009 , G06F9/30098 , G06F9/30145 , G06F9/3016 , G06F9/3802 , G06F9/3834 , G06F9/384 , G06F9/3842 , G06F9/466 , G06F9/467 , G06F11/1407 , G06F11/2236 , G06F11/25 , G06F11/263 , G06F12/0811 , G06F12/0828 , G06F12/084 , G06F12/0862 , G06F12/0875 , G06F12/0897 , G06F2212/1032 , G06F2212/20 , G06F2212/283 , G06F2212/314 , G06F2212/452 , G06F2212/602 , G06F2212/608 , G06F2212/621 , G11C7/1072
Abstract: Novel instructions, logic, methods and apparatus are disclosed to test transactional execution status. Embodiments include decoding a first instruction to start a transactional region. Responsive to the first instruction, a checkpoint for a set of architecture state registers is generated and memory accesses from a processing element in the transactional region associated with the first instruction are tracked. A second instruction to detect transactional execution of the transactional region is then decoded. An operation is executed, responsive to decoding the second instruction, to determine if an execution context of the second instruction is within the transactional region. Then responsive to the second instruction, a first flag is updated. In some embodiments, a register may optionally be updated and/or a second flag may optionally be updated responsive to the second instruction.
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公开(公告)号：US20150263914A1
公开(公告)日：2015-09-17
申请号：US14726680
申请日：2015-06-01
Applicant: Openconnect Systems, lncorporated
Inventor： Eric P. Armstrong , Stuart H. Burris, JR. , Christopher Raymond Houck
CPC classification number: H04L43/06 , G06F11/28 , G06F11/32 , G06F11/3447 , G06F11/3476 , G06F2201/835 , G06F2201/87 , H04L43/00 , H04L43/04 , H04L43/045 , H04L43/106 , H04L43/16
Abstract: In certain embodiments, a method for modeling interactions with a computer system includes collecting interaction information for each of a number of interaction sessions with a computer system, each interaction session being associated with a corresponding agent system and including one or more states and one or more state transitions. The interaction information for an interaction session includes data for the one or more states and the one or more state transitions of the interaction session. The method further includes, for each of the interaction sessions, identifying the one or more states encountered during the interaction session based on the collected interaction information and generating, based on the one or more states encountered during the interaction session, a trace of the interaction session. The method further includes generating, based on the traces of the interaction sessions, a model of the interaction sessions, the model including the traces for each of the interaction sessions.
Abstract translation: 在某些实施例中，用于建模与计算机系统的交互的方法包括收集与计算机系统的多个交互会话中的每一个的交互信息，每个交互会话与相应的代理系统相关联并且包括一个或多个状态和一个或多个 状态转换。 交互会话的交互信息包括一个或多个状态的数据和交互会话的一个或多个状态转换。 该方法还包括针对每个交互会话，基于所收集的交互信息识别在交互会话期间遇到的一个或多个状态，并且基于在交互会话期间遇到的一个或多个状态生成该交互的踪迹 会话 该方法还包括基于交互会话的轨迹生成交互会话的模型，模型包括每个交互会话的跟踪。
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公开(公告)号：US09135082B1
公开(公告)日：2015-09-15
申请号：US13112945
申请日：2011-05-20
Applicant: Tianwei Sheng , Neil A. Vachharajani , Stephane Eranian , Robert Hundt
Inventor： Tianwei Sheng , Neil A. Vachharajani , Stephane Eranian , Robert Hundt
CPC classification number: G06F9/524 , G06F8/458 , G06F11/28 , G06F11/36 , G06F11/3632
Abstract: A race detection mechanism can include running threads of a multithreaded program on a processor, the program being configured to produce locksets each of which indicate a set of one or more locks that a thread holds at a point in time. The mechanism can cause a performance monitoring unit included in the processor to monitor memory accesses caused by the threads and to produce samples based on the memory accesses, the samples being indicative of an accessed memory location. The mechanism can detect an existence of a data race condition based on the samples and the locksets. Detecting can include identifying a protected access to a memory location by a first thread of the threads and identifying an unprotected access to the memory location by a second thread of the threads. The process selectively outputs an indication of the data race condition.
Abstract translation: 竞争检测机制可以包括在处理器上运行多线程程序的线程，该程序被配置为产生锁定器，每个锁定器指示线程在某个时间点保持的一个或多个锁的集合。 该机制可以使处理器中包括的性能监视单元监视由线程引起的存储器访问并且基于存储器访问产生样本，该样本表示访问的存储器位置。 该机制可以基于样本和锁定点来检测数据竞争条件的存在。 检测可以包括通过线程的第一线程识别对存储器位置的受保护的访问，并且由线程的第二线程识别对存储器位置的不受保护的访问。 该过程选择性地输出数据竞争条件的指示。
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