公开(公告)号：US20180190637A1

公开(公告)日：2018-07-05

申请号：US15739260

申请日：2016-07-14

Applicant: Mitsumi Electric Co., Ltd.

Inventor： Makoto KITAZUME ,  Toshiki KOMIYAMA

IPC: H01L25/18 ,  H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/31 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/162 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/15791 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/284 ,  H05K3/4007 ,  H05K2201/10674 ,  H05K2203/025 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: The module is implemented on a circuit board, the module including a wiring board; an electronic component implemented on a first surface of the wiring board; an external connection electrode formed on a second surface of the wiring board; a solder bump connected to the external connection electrode; a bare chip implemented facedown on the second surface of the wiring board; and a resin covering a surface and a side surface of the bare chip and a side surface of the solder bump on the second surface of the wiring board, wherein a reverse surface of the bare chip and a connection surface of the solder bump are exposed from the resin such that the reverse surface of the bare chip and the connection surface of the solder bump are on a same plane, and wherein the module is implemented on the circuit board so that the reverse surface of the bare chip and the connection surface of the solder bump face the circuit board.

公开(公告)号：US09984979B2

公开(公告)日：2018-05-29

申请号：US15297831

申请日：2016-10-19

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dae Hyun Park ,  Han Kim ,  Kang Heon Hur ,  Young Gwan Ko ,  Jung Ho Shim

IPC: H05K7/00 ,  H01L23/538 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00 ,  H01L21/683 ,  H01L23/48 ,  H01L23/00 ,  H05K1/02 ,  H05K1/18 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6836 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2221/68386 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/16238 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

公开(公告)号：US20180124928A1

公开(公告)日：2018-05-03

申请号：US15842310

申请日：2017-12-14

Applicant: HSIO Technologies, LLC

Inventor： James J. Rathburn

IPC: H05K3/46 ,  H05K3/00 ,  H05K3/18 ,  H05K3/06 ,  H05K3/42 ,  H01L21/48

CPC classification number: H05K3/4623 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/064 ,  H05K3/188 ,  H05K3/425 ,  H05K3/429 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0141 ,  H05K2201/096 ,  H05K2201/10674

Abstract: A method of making a fusion bonded circuit structure. Each major surface of an LCP substrate is provided with a seed layers of a conductive material. Resist layers are deposited on the seed layers. The resist layers are processed to create recesses corresponding to a desired circuitry layers on each side of the LCP substrate. The recesses expose portions of the seed layers of conductive material. The LCP substrate is electroplated to simultaneously create conductive traces defined by the first recesses on both sides of the LCP substrate. The resist layers are removed to reveal the conductive traces. The LCP substrate is etched to remove exposed portions of the seed layers adjacent the conductive traces. LCP layers are fusion bonded to the major surfaces of the LCP substrate to encapsulate the conductive traces in an LCP material. The LCP layers can be laser drilled to expose the conductive traces.

公开(公告)号：US20180116051A1

公开(公告)日：2018-04-26

申请号：US15847852

申请日：2017-12-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US09935053B2

公开(公告)日：2018-04-03

申请号：US15409766

申请日：2017-01-19

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Satoshi Shiraki ,  Koichi Tanaka

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H05K1/14 ,  H01L21/48 ,  H05K3/34

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3142 ,  H01L23/5384 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/042 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion that selectively exposes the first pad, and a connection pad formed on the first solder resist layer, and electrically connected to the first pad; a second substrate, stacked on the first substrate, including a second pad, and a second solder resist layer formed on the second pad and provided with a second open portion that selectively exposes the second pad; an electronic component mounted on the first substrate and sandwiched between the first substrate and the second substrate; and a substrate connection member that electrically connects the connection pad and the second pad with each other, the diameter of the connection pad being larger than each of the diameter of the first pad and the diameter of the second open portion.

公开(公告)号：US20180082923A1

公开(公告)日：2018-03-22

申请号：US15811038

申请日：2017-11-13

Applicant: Nuvotronics, Inc

Inventor： Jean-Marc Rollin ,  David W. Sherrer

IPC: H01L23/373 ,  H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L23/528 ,  H01L23/58

CPC classification number: H01L23/373 ,  H01L23/5286 ,  H01L23/552 ,  H01L23/562 ,  H01L23/58 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/85444 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01P3/06 ,  H01P11/005 ,  H05K1/0221 ,  H05K1/0224 ,  H05K1/0272 ,  H05K3/4092 ,  H05K3/4661 ,  H05K2201/09809 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2203/0733 ,  H05K2203/308 ,  Y02P70/611 ,  Y10T29/49002 ,  Y10T29/49018 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are integrated electronic components which include a waveguide microstructure formed by a sequential build process and an electronic device, and methods of forming such integrated electronic components. The microstructures have particular applicability to devices for transmitting electromagnetic energy and other electronic signals.

公开(公告)号：US09918386B2

公开(公告)日：2018-03-13

申请号：US15489563

申请日：2017-04-17

Applicant: Skyworks Solutions, Inc.

Inventor： Darren Roger Frenette ,  George Khoury ,  Leslie Paul Wallis ,  Lori Ann DeOrio

IPC: H05K1/18 ,  H01L23/488 ,  H04B1/40 ,  H03F3/195 ,  H03F3/213 ,  H03H7/06 ,  H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/66

CPC classification number: H05K1/181 ,  H01L23/3107 ,  H01L23/66 ,  H01L24/16 ,  H01L24/48 ,  H01L25/16 ,  H01L25/18 ,  H01L41/0475 ,  H01L41/113 ,  H01L2223/6644 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48195 ,  H01L2224/48225 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/146 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/19107 ,  H03B5/32 ,  H03F3/195 ,  H03F3/213 ,  H03F2200/451 ,  H03H7/06 ,  H03H9/0547 ,  H03H2001/0021 ,  H04B1/40 ,  H05K2201/1006 ,  H05K2201/10098 ,  H05K2201/10674 ,  H01L2224/45099

Abstract: A packaged module for use in a wireless communication device has a substrate supporting an integrated circuit die that includes at least a microprocessor and radio frequency receiver circuitry and a stacked filter assembly configured as a filter circuit that is in communication with the radio frequency receiver circuitry. The stacked filter assembly includes a plurality of passive components, where each passive component is packaged as a surface mount device. At least one passive component is in direct communication with the substrate and at least another passive component is supported above the substrate by the at least one passive component that is in the direct communication with the substrate.

公开(公告)号：US09905438B2

公开(公告)日：2018-02-27

申请号：US15466063

申请日：2017-03-22

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Ming-Chen Sun ,  Chun-Hsien Lin ,  Tzu-Chieh Shen ,  Shih-Chao Chiu ,  Yu-Cheng Pai

IPC: H01L21/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8182 ,  H01L2924/15313 ,  H05K1/111 ,  H05K3/20 ,  H05K3/205 ,  H05K3/428 ,  H05K2201/0376 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/014

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

公开(公告)号：US09893045B2

公开(公告)日：2018-02-13

申请号：US14971291

申请日：2015-12-16

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Seng Guan Chow ,  Seung Uk Yoon ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/538 ,  H01L25/10 ,  H05K1/18 ,  H05K3/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/16 ,  H01L21/48 ,  H01L23/29 ,  H01L23/31 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/486 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/25 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06131 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/21 ,  H01L2224/2105 ,  H01L2224/215 ,  H01L2224/22 ,  H01L2224/221 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24101 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/245 ,  H01L2224/25171 ,  H01L2224/27002 ,  H01L2224/29 ,  H01L2224/2902 ,  H01L2224/29101 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48175 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/82104 ,  H01L2224/82106 ,  H01L2224/83005 ,  H01L2224/83191 ,  H01L2224/8385 ,  H01L2224/94 ,  H01L2224/95001 ,  H01L2224/97 ,  H01L2225/06548 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/107 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/078 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H05K1/186 ,  H05K3/007 ,  H05K2201/10674 ,  H01L2224/81 ,  H01L2924/01014 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.

公开(公告)号：US09847308B2

公开(公告)日：2017-12-19

申请号：US14566185

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Rajasekaran Swaminathan ,  Ravindranath V. Mahajan

IPC: H01L23/00 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/742 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/1132 ,  H01L2224/11418 ,  H01L2224/1147 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13147 ,  H01L2224/13294 ,  H01L2224/133 ,  H01L2224/13311 ,  H01L2224/13316 ,  H01L2224/13355 ,  H01L2224/13357 ,  H01L2224/1336 ,  H01L2224/13387 ,  H01L2224/13411 ,  H01L2224/13447 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/16503 ,  H01L2224/75264 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81222 ,  H01L2224/81409 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81455 ,  H01L2224/81464 ,  H01L2224/8181 ,  H01L2224/81815 ,  H01L2924/01026 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3511 ,  H01L2924/3512 ,  H01L2924/35121 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/3494 ,  H05K2201/0341 ,  H05K2201/083 ,  H05K2201/10674 ,  H05K2203/104 ,  Y02P70/613 ,  H01L2924/01082 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/05381 ,  H01L2924/053 ,  H01L2924/0532 ,  H01L2924/01056

Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.