公开(公告)号：US20160127027A1

公开(公告)日：2016-05-05

申请号：US14931103

申请日：2015-11-03

Applicant: Maxlinear, Inc.

Inventor： Curtis Ling ,  Sheng Ye

IPC: H04B7/08 ,  H04B10/40 ,  H04B1/40 ,  H01Q3/24 ,  H04B1/7097

CPC classification number: H04B7/086 ,  H01Q3/24 ,  H01Q3/247 ,  H01Q3/267 ,  H04B7/0617 ,  H04B10/25752 ,  H04B10/40 ,  H04B10/43 ,  H04B17/0085 ,  H04B17/12 ,  H04B2201/709709

Abstract: Each of a plurality of modules comprises a respective one of a plurality of antenna elements, and each of a subset of the plurality of modules comprising a respective one of a plurality of transceivers, wherein the plurality of modules are interconnected via one or more communication links. The circuitry may be operable to receive a calibration signal via the plurality of antenna elements, determine, for each one of the antenna elements, a time and/or phase of arrival of the calibration signal, calculate, based on the time and/or phase of arrival of the calibration signal at each of the plurality of antenna elements, electrical distances between the plurality of antenna elements on the one or more communication links, and calculate beamforming coefficients for use with the plurality of antenna elements based on the electrical distances.

Abstract translation: 多个模块中的每一个包括多个天线元件中的相应一个，并且多个模块的子集中的每一个包括多个收发器中的相应一个，其中多个模块经由一个或多个通信链路 。 该电路可操作以经由多个天线元件接收校准信号，为每个天线元件确定校准信号的到达时间和/或相位，基于时间和/或相位来计算 所述校准信号到达所述多个天线元件中的每一个时，所述一个或多个通信链路上的所述多个天线元件之间的电距离，以及基于所述电气距离计算与所述多个天线元件一起使用的波束成形系数。

公开(公告)号：US09320019B2

公开(公告)日：2016-04-19

申请号：US13862336

申请日：2013-04-12

Applicant: MaxLinear, Inc.

Inventor： Timothy Gallagher ,  Curtis Ling ,  Alan Trerise ,  Kishore Seendripu

IPC: H04W72/04 ,  H04W16/02

CPC classification number: H04W72/04 ,  H04W16/02 ,  H04W84/12 ,  H04W88/08

Abstract: A WiFi device, which utilizes full spectrum capture, captures signals over a wide spectrum including one or more WiFi frequency bands and extracts one or more WiFi channels from the captured signals. The AP analyzes the extracted WiFi channels and aggregates a plurality of blocks of WiFi channels to create one or more aggregated WiFi channels based on the analysis. The WiFi frequency bands comprise 2.4 GHz and 5 GHz WiFi frequency bands. The AP determines one or more characteristics of the extracted WiFi channels based on the analysis. The determined characteristics comprise noise, interference, fading and blocker information. The AP generates a channel map comprising at least the extracted one or more WiFi channels based on the determined characteristics. The AP dynamically and/or adaptively senses the extracted one or more WiFi channels and updates the determined characteristics of the extracted WiFi channels.

Abstract translation: 使用全频谱捕获的WiFi设备在包括一个或多个WiFi频带的广谱中捕获信号，并从捕获的信号中提取一个或多个WiFi信道。 AP分析提取的WiFi信道并且聚合多个WiFi信道块以基于分析来创建一个或多个聚合的WiFi信道。 WiFi频段包括2.4GHz和5GHz WiFi频带。 AP基于分析确定提取的WiFi信道的一个或多个特征。 所确定的特征包括噪声，干扰，衰落和阻塞信息。 基于所确定的特征，AP产生至少包括所提取的一个或多个WiFi信道的频道映射。 AP动态地和/或自适应地感测所提取的一个或多个WiFi信道，并更新确定的提取的WiFi信道的特性。

公开(公告)号：US20160099737A1

公开(公告)日：2016-04-07

申请号：US14966660

申请日：2015-12-11

Applicant: MaxLinear, Inc.

Inventor： Kishore Seendripu ,  Raymond Montemayor ,  Sheng Ye ,  Glenn Chang ,  Curtis Ling

IPC: H04B1/30 ,  H03D7/14 ,  H03D7/16

CPC classification number: H04B1/26 ,  H03D3/007 ,  H03D3/008 ,  H03D3/009 ,  H03D7/14 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1475 ,  H03D7/165 ,  H03D7/166 ,  H03D2200/0086 ,  H03H11/22 ,  H04B1/10 ,  H04B1/109 ,  H04B1/12 ,  H04B1/30 ,  H04B15/00 ,  H04J1/18 ,  H04L27/34

Abstract: Receiver architectures and methods of processing harmonic rich input signals employing harmonic suppression mixers are disclosed herein. The disclosed receivers, mixers, and methods enable a receiver to achieve the advantages of switching mixers while greatly reducing the mixer response to the undesired harmonics. A harmonic mixer can include a plurality of mixers coupled to an input signal. A plurality of phases of a local oscillator signal can be generated from a single local oscillator output. Each of the phases can be used to drive an input of one of the mixers. The mixer outputs can be combined to generate a frequency converted output that has harmonic rejection.

公开(公告)号：US20160098321A1

公开(公告)日：2016-04-07

申请号：US14967653

申请日：2015-12-14

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Timothy Gallagher

IPC: G06F11/10 ,  G06F3/06 ,  H03M13/11

CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0685 ,  G06F11/1012 ,  H03M13/1102 ,  H03M13/1105 ,  H03M13/1148 ,  H03M13/152 ,  H03M13/2906

Abstract: A low density parity check (LDPC) decoder integrated on a single semiconductor substrate may comprise one or more arrays of first-type memory cells and one or more arrays of second-type memory cells. The LDPC decoder may be configured to store intrinsic messages in the array of first-type cells and to store extrinsic messages in the array of second-type cells. The first-type cells may be a first one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO. The second-type cells may be a second one of: static random access memory (SRAM) cells, refreshed dynamic random access memory (DRAM) cells, non-refreshed DRAM cells configured as a FIFO, and non-refreshed DRAM cells not configured as a FIFO.

Abstract translation: 集成在单个半导体衬底上的低密度奇偶校验（LDPC）解码器可以包括一个或多个第一类型存储器单元阵列和一个或多个第二类型存储器单元阵列。 LDPC解码器可以被配置为将固有消息存储在第一类型单元阵列中，并将外部消息存储在第二类型单元阵列中。 第一类型的单元可以是静态随机存取存储器（SRAM）单元，更新的动态随机存取存储器（DRAM）单元，被配置为FIFO的非刷新DRAM单元以及未被配置为 一个FIFO。 第二类型单元可以是静态随机存取存储器（SRAM）单元，更新的动态随机存取存储器（DRAM）单元，被配置为FIFO的未刷新DRAM单元以及未被配置为 一个FIFO。

公开(公告)号：US09277536B2

公开(公告)日：2016-03-01

申请号：US13862339

申请日：2013-04-12

Applicant: Maxlinear, Inc.

Inventor： Timothy Gallagher ,  Curtis Ling ,  Alan Trerise ,  Kishore Seendripu

IPC: H04W72/04 ,  H04W16/02

CPC classification number: H04W72/04 ,  H04W16/02 ,  H04W84/12 ,  H04W88/08

Abstract: A single receiver is operable to utilize full spectrum capture to capture signals over a wide spectrum comprising a plurality of WiFi frequency bands, extract one or more WiFi channels from said captured signals and aggregate a plurality of blocks of said WiFi channels to create one or more aggregated WiFi channels. The WiFi frequency bands include 2.4 GHz and 5 GHz WiFi frequency bands. A plurality of blocks of the WiFi channels may be aggregated from contiguous blocks of spectrum and/or non-contiguous blocks of spectrum in one or more of said plurality of WiFi frequency bands. One or more non-WiFi channels may be filtered out from the captured signals. One or more aggregated WiFi channels may be assigned to one or more WiFi enabled communication devices. At least a portion of the one or more aggregated WiFi channels may be dynamically assigned to one or more other WiFi enabled communication devices.

Abstract translation: 单个接收器可操作以利用全频谱捕获来在包括多个WiFi频带的宽频谱上捕获信号，从所述捕获的信号中提取一个或多个WiFi信道并聚合所述WiFi信道的多个块以创建一个或多个 聚合的WiFi频道。 WiFi频段包括2.4 GHz和5 GHz WiFi频段。 WiFi信道的多个块可以从所述多个WiFi频带中的一个或多个中的频谱和/或非连续的频谱块的连续块聚合。 可以从捕获的信号中滤出一个或多个非WiFi信道。 可以将一个或多个聚合的WiFi信道分配给一个或多个启用WiFi的通信设备。 一个或多个聚合的WiFi信道的至少一部分可以被动态分配给一个或多个其他支持WiFi的通信设备。

公开(公告)号：US09247274B2

公开(公告)日：2016-01-26

申请号：US14154234

申请日：2014-01-14

Applicant: MaxLinear, Inc

Inventor： Sridhar Ramesh ,  Curtis Ling ,  Jingnong Yang

IPC: H04N21/2385 ,  H04N21/61 ,  H04N7/10 ,  H04H20/63 ,  H04H40/90

CPC classification number: H04N21/4383 ,  H04H20/63 ,  H04H40/90 ,  H04N7/106 ,  H04N21/2385 ,  H04N21/615

Abstract: A receiver includes a plurality of input paths for receiving and processing a plurality of input RF signals. The input paths isolate one or more portions of corresponding ones of the received input RF signals, and combine the isolated portions of the corresponding ones of the received input RF signals onto one or more output signals. A bandwidth of the isolated portions of the corresponding ones of the received input RF signals and a bandwidth of the output signals are variable. The isolated portions of the corresponding ones of the received plurality of input RF signals are extracted and utilized to generate the output signals. The portions of the corresponding ones of the received plurality of input RF signals may be mapped into one or more channel slots in the time domain. The channel slots may be assigned in the frequency domain to one or more frequency bins.

Abstract translation: 接收机包括用于接收和处理多个输入RF信号的多个输入路径。 所述输入路径隔离所接收的输入RF信号中相应的一个的一个或多个部分，并且将所接收的输入RF信号中相应的一个的隔离部分组合到一个或多个输出信号上。 所接收的输入RF信号中相应的一个的隔离部分的带宽和输出信号的带宽是可变的。 接收到的多个输入RF信号中相应的一部分的隔离部分被提取并用于产生输出信号。 所接收的多个输入RF信号中相应的部分可被映射到时域中的一个或多个信道时隙。 信道时隙可以在频域中分配给一个或多个频率仓。

公开(公告)号：US20150312051A1

公开(公告)日：2015-10-29

申请号：US14695261

申请日：2015-04-24

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Timothy Gallagher

IPC: H04L12/28 ,  H04L12/12

CPC classification number: H04L12/2863 ,  H04L12/12 ,  H04L12/2801 ,  H04L12/2861 ,  H04L12/2865 ,  H04L47/10 ,  H04L47/22 ,  H04L47/41 ,  Y02D50/30

Abstract: Methods and systems are provided for power control in communications devices. Bonding of channels in communication devices may be dynamically adjusted, such as responsive to requests for bandwidth adjustment. For example, bonded channel configurations may be adjusted based on power, such as to single channel configurations (or to channel configurations with small number of channels, such as relative to current configurations) for low power operations. Components (or functions thereof) used in conjunction with receiving and/or processing bonded channels may be dynamically adjusted. Such dynamic adjustments may be performed, for example, such as to maintain required synchronization and system information to facilitate rapid data transfer resumption upon demand.

Abstract translation: 为通信设备中的功率控制提供了方法和系统。 可以动态调整通信设备中的信道的绑定，例如响应于带宽调整的请求。 例如，可以基于功率来调整绑定通道配置，例如用于低功率操作的单通道配置（或具有少量通道的通道配置，例如相对于当前配置）。 可以动态地调整与接收和/或处理绑定信道一起使用的组件（或其功能）。 可以执行这种动态调整，例如，以便维持所需的同步和系统信息以便于在需要时恢复快速数据传输。

公开(公告)号：US09153310B2

公开(公告)日：2015-10-06

申请号：US14156792

申请日：2014-01-16

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling

IPC: G11C7/00 ,  G11C11/406 ,  G11C29/02 ,  G11C29/42 ,  G11C29/50 ,  G11C29/04

CPC classification number: G11C11/406 ,  G11C11/404 ,  G11C11/40611 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C29/42 ,  G11C29/50016 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2207/104 ,  G11C2211/4062

Abstract: An integrated circuit may comprise a digital logic circuit, a memory refresh circuit, a first one or more dynamic random access memory (DRAM) cells, and a second one or more DRAM cells. The first DRAM cell(s) may be refreshed by the memory refresh circuit whereas the second DRAM cell(s) is not refreshed by any memory refresh circuit. Each of the first DRAM cell(s) and the second DRAM cell(s) may be a one-transistor cell. The first DRAM cell(s) may be used for storage of data which is overwritten at less than a threshold frequency. The second DRAM cell(s) may be used for storage of data which is overwritten at greater than the threshold frequency. A rate at which the first DRAM cell(s) are refreshed may be adjusted during run-time of the integrated circuit.

Abstract translation: 集成电路可以包括数字逻辑电路，存储器刷新电路，第一个一个或多个动态随机存取存储器（DRAM）单元和第二个一个或多个DRAM单元。 第一DRAM单元可以被存储器刷新电路刷新，而第二DRAM单元不被任何存储器刷新电路刷新。 第一DRAM单元和第二DRAM单元中的每一个可以是单晶体管单元。 第一DRAM单元可用于存储以小于阈值频率覆盖的数据。 第二DRAM单元可用于存储以大于阈值频率覆盖的数据。 可以在集成电路的运行时间期间调整第一DRAM单元刷新的速率。

公开(公告)号：US09124339B2

公开(公告)日：2015-09-01

申请号：US14245589

申请日：2014-04-04

Applicant: MaxLinear, Inc.

Inventor： Glenn Chang ,  Sridhar Ramesh ,  Curtis Ling

IPC: H04L27/04 ,  H03K9/00 ,  H04B1/16 ,  G06F7/00 ,  H01L25/00

CPC classification number: H04N21/2187 ,  G06F7/00 ,  H01L25/00 ,  H01L2924/0002 ,  H01Q13/206 ,  H01Q21/0012 ,  H04B1/10 ,  H04B1/16 ,  H04B1/18 ,  H04L12/2838 ,  H04L2012/2849 ,  H04N21/2221 ,  H04N21/6118 ,  H04N21/6193 ,  H01L2924/00

Abstract: Methods and systems are provided for loop-through for multi-chip communication systems. Receiver circuitry, that is operable to receive one or more input feeds, may comprise a plurality of chips, each of which may be configurable to generate a corresponding output comprising one or more feed elements (e.g., channels) extracted from the input feed(s). However, only a first chip may be operable to handle reception and/or initial processing of the one or more input feeds, with each one of the remaining chips processing a loop-through feed generated by the first chip, in order to generate the corresponding output of that chip. The first chip generates the loop-through feed based on the one or more input feeds, such as after the initial processing thereof in the first chip. Generating the loop-through feed may comprise applying channelization (e.g., separately for each remaining chip), switching based processing, and/or interfacing based processing.

Abstract translation: 提供了用于多芯片通信系统的循环的方法和系统。 可操作以接收一个或多个输入馈送的接收器电路可以包括多个芯片，每个芯片可以被配置为生成包括从输入馈送提取的一个或多个馈送元件（例如，信道）的相应输出 ）。 然而，仅第一芯片可操作以处理一个或多个输入馈送的接收和/或初始处理，其中每个剩余芯片处理由第一芯片产生的环通馈送，以便产生相应的 该芯片的输出。 第一芯片基于一个或多个输入馈送（例如在第一芯片中的初始处理之后）产生环通馈送。 产生环通馈送可以包括对信道化（例如，针对每个剩余的芯片单独地）进行信道化，基于切换的处理和/或基于接口的处理。

公开(公告)号：US09094269B2

公开(公告)日：2015-07-28

申请号：US14224123

申请日：2014-03-25

Applicant: MaxLinear, Inc.

Inventor： Curtis Ling ,  Timothy Leo Gallagher

IPC: H04K1/02 ,  H04L25/03 ,  H04L25/49 ,  H04L27/26

CPC classification number: H04L27/2614

Abstract: A transmitter may comprise a first domain translation circuit, a first PAPR suppression circuit, and a descriptor generation circuit. The first domain translation circuit may convert a plurality of frequency-domain symbols of a first OFDM symbol to a corresponding plurality of first time-domain signals. The first PAPR suppression circuit may group the plurality of first time-domain signals into a plurality of sub-bands of the first time-domain. The first PAPR suppression circuit may invert one or more of the sub-bands of the first time-domain signals according to a value of a first descriptor. The descriptor generation circuit may determine the value of the first descriptor using an iterative process in which each iteration comprises random selection of a value of the first descriptor, determination of a PAPR of the first OFDM symbol processed using the randomly-selected value, and determination of whether said PAPR meets one or more determined criteria.

Abstract translation: 发射机可以包括第一域转换电路，第一PAPR抑制电路和描述符生成电路。 第一域转换电路可以将第一OFDM符号的多个频域符号转换为对应的多个第一时域信号。 第一PAPR抑制电路可以将多个第一时域信号分组成第一时域的多个子带。 第一PAPR抑制电路可以根据第一描述符的值来反转第一时域信号的一个或多个子带。 描述符生成电路可以使用迭代过程来确定第一描述符的值，其中每个迭代包括对第一描述符的值的随机选择，使用随机选择的值处理的第一OFDM符号的PAPR的确定和确定 是否所述PAPR是否满足一个或多个确定的标准。