公开(公告)号：US20120100719A1

公开(公告)日：2012-04-26

申请号：US13377319

申请日：2010-06-17

Applicant: Christophe Constancias ,  Bernard Dalzotto ,  Frank Fournel ,  Philippe Michallon ,  Hubert Moriceau ,  Valerie Pouteau

Inventor： Christophe Constancias ,  Bernard Dalzotto ,  Frank Fournel ,  Philippe Michallon ,  Hubert Moriceau ,  Valerie Pouteau

IPC: H01L21/31 ,  G01N3/08

CPC classification number: B81C1/00158 ,  B81B2201/0264 ,  B81B2201/047 ,  B81C2201/017

Abstract: A method for determining a minimum tension compensation stress which will have a membrane of a thickness of less than or equal to one micrometer, secured to a frame, having, in the absence of any external stress, a desired deflection. The membrane can be made as planar as possible in absence of any external stress, and its thickness can be less than or equal to one micrometer.

Abstract translation: 一种用于确定最小张力补偿应力的方法，其将具有小于或等于1微米厚度的膜，固定到框架，在没有任何外部应力的情况下具有期望的偏转。 膜可以在没有任何外部应力的情况下制成尽可能平坦的，并且其厚度可以小于或等于1微米。

公开(公告)号：US08164153B2

公开(公告)日：2012-04-24

申请号：US12473179

申请日：2009-05-27

Applicant: Xiaoyi Ding ,  Jeffrey J. Frye ,  Gregory A. Miller

Inventor： Xiaoyi Ding ,  Jeffrey J. Frye ,  Gregory A. Miller

IPC: H01L29/82

CPC classification number: G01L9/0042 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/00873 ,  G01L9/0052 ,  G01L9/0055 ,  H01L21/6835 ,  H01L21/6836 ,  H01L2221/68327 ,  H01L2221/6835 ,  H01L2221/68381

Abstract: Ultra-thin semiconductor devices, including piezoresistive sensing elements can be formed in a wafer stack that facilitates handling many thin device dice at a wafer level. Three embodiments are provided to form the thin dice in a wafer stack using three different fabrication techniques that include anodic bonding, adhesive bonding and fusion bonding. A trench is etched around each thin die to separate the thin die from others in the wafer stack. A tether layer, also known as a tether, is used to hold thin dice or dice in a wafer stack. Such as wafer stack holds many thin dice together at a wafer level for handling and enables easier die picking in packaging processes.

Abstract translation: 包括压阻感测元件的超薄半导体器件可以形成在晶片堆叠中，这有助于在晶片级处理许多薄的器件管芯。 提供三个实施例以使用三种不同的制造技术在晶片叠层中形成薄的骰子，这些制造技术包括阳极接合，粘结和粘合。 在每个薄模具周围蚀刻沟槽，以将薄晶片与晶片堆叠中的其它芯片分离。 系绳层（也称为系绳）用于将薄骰子或骰子保持在晶片堆叠中。 例如晶片堆叠在晶片级将许多薄的骰子保持在一起以进行处理，并且能够在包装过程中更容易地进行拣选。

公开(公告)号：US20120049298A1

公开(公告)日：2012-03-01

申请号：US12873195

申请日：2010-08-31

Applicant: Mark E. Schlarmann ,  Yizhen Lin

Inventor： Mark E. Schlarmann ,  Yizhen Lin

IPC: H01L29/84 ,  H01L21/02

CPC classification number: B81C1/00309 ,  B81B2201/0264 ,  B81C2203/0154 ,  G01L9/0073 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/181 ,  H01L2924/1815 ,  H04R19/005 ,  H04R19/04 ,  H04R31/00 ,  H04R2201/003 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A MEMS device assembly (20) includes a MEMS die (22) and an integrated circuit (IC) die (24). The MEMS die (22) includes a MEMS device (36) formed on a substrate (38) and a cap layer (34). A packaging process (72) entails forming the MEMS device (36) on the substrate (38) and removing a material portion of the substrate (38) surrounding the device (36) to form a cantilevered substrate platform (46) at which the MEMS device (36) resides. The cap layer (34) is coupled to the substrate (38) overlying the MEMS device (36). The MEMS die (22) is electrically interconnected with the IC die (24). Molding compound (32) is applied to substantially encapsulate the MEMS die (22), the IC die (24), and interconnects (30) that electrically interconnect the MEMS device (22) with the IC die (24). The cap layer (34) prevents the molding compound (32) from contacting the MEMS device (36).

Abstract translation: MEMS器件组件（20）包括MEMS管芯（22）和集成电路（IC）管芯（24）。 MEMS管芯（22）包括形成在衬底（38）和盖层（34）上的MEMS器件（36）。 包装工艺（72）需要在衬底（38）上形成MEMS器件（36）并且去除围绕器件（36）的衬底（38）的材料部分以形成悬臂衬底平台（46），在该悬臂衬底平台 设备（36）驻留。 盖层（34）耦合到覆盖在MEMS器件（36）上的衬底（38）。 MEMS管芯（22）与IC管芯（24）电连接。 施加成型化合物（32）以将MEMS管芯（22），IC管芯（24）以及将MEMS器件（22）与IC管芯（24）电连接的互连件（30）基本上封装。 盖层（34）防止模塑料（32）与MEMS装置（36）接触。

公开(公告)号：US08123963B2

公开(公告)日：2012-02-28

申请号：US12152241

申请日：2008-05-12

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

IPC: H01L21/302 ,  B81C1/00

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00595 ,  B81C2201/0115 ,  G01L9/0045 ,  H01L21/3063

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

Abstract translation: 一种制造半导体部件的方法包括在所述半导体部件的p掺杂层中形成n掺杂层，其中所述n掺杂层包括以下中的至少一种：筛状层或网状层。 该方法还包括在n掺杂层的材料之间对p-掺杂层进行腐蚀蚀刻以形成顶部电极，以及在n-掺杂层下方形成空腔。

公开(公告)号：US20120021550A1

公开(公告)日：2012-01-26

申请号：US13176371

申请日：2011-07-05

Applicant: CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

Inventor： CHRISTEL DIEPPEDALE ,  STEPHAN BOREL ,  BRUNO REIG ,  HENRI SIBUET

IPC: H01L21/02

CPC classification number: B81C1/00158 ,  B81B2201/018 ,  B81B2201/0264 ,  B81B2203/0118 ,  B81B2203/0361 ,  B81C1/00492 ,  B81C2201/0178 ,  H01H1/0036

Abstract: The fabrication of a semiconductor fixed structure defining a volume, for example of a MEMS micro electro-mechanical system includes, determining thicknesses beforehand depending on the functional distances associated with elements. At least one element is formed on a substrate by thermal oxidation of the substrate so as to form an oxide layer followed by selective etching of the oxide layer so as to define the volume in an etched portion by baring the underlying substrate so as to define the element in an unetched portion, and later oxidation of the substrate so as to form an oxide layer, in order to obtain the elements at the functional distances.

Abstract translation: 限定体积的半导体固定结构（例如MEMS微机电系统）的制造包括：根据与元件相关联的功能距离预先确定厚度。 通过衬底的热氧化在衬底上形成至少一个元件，以便形成氧化物层，然后选择性地蚀刻氧化物层，以便通过掩埋下面的衬底限定蚀刻部分中的体积，从而限定 元素在未蚀刻部分中，并且随后氧化基底以形成氧化物层，以便在功能距离处获得元件。

公开(公告)号：US08072083B1

公开(公告)日：2011-12-06

申请号：US12657425

申请日：2010-01-20

Applicant: Roger D. St. Amand ,  ChangSuk Han ,  YounSang Kim ,  KyungRok Park ,  Vladimir Perelman

Inventor： Roger D. St. Amand ,  ChangSuk Han ,  YounSang Kim ,  KyungRok Park ,  Vladimir Perelman

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L23/49582 ,  B81B2201/0264 ,  B81B2207/07 ,  B81C1/0023 ,  B81C2201/019 ,  G01L19/0084 ,  G01L19/141 ,  H01L23/49548 ,  H01L23/49816 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L27/14618 ,  H01L2224/27013 ,  H01L2224/274 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29298 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48599 ,  H01L2224/4899 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/83051 ,  H01L2224/83139 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A film-on-wire spacer covers an entire upper surface of a lower electronic component. Accordingly, an upper electronic component is supported above bond pads and lower bond wires of the lower electronic component. This decreases the stress on the upper electronic component, e.g., during wirebonding, and thus decreases the chance of cracking the upper electronic component. Further, the lower bond wires are enclosed in and protected by the film-on-wire spacer. Further, the film-on-wire spacer is thin resulting in a minimum height of the stacked electronic component package.

Abstract translation: 电影在线隔离物覆盖下电子元件的整个上表面。 因此，上部电子部件被支撑在下部电子部件的接合焊盘和下部接合线之上。 这降低了上电子部件上的应力，例如在引线键合期间，因此减少了上部电子部件破裂的可能性。 此外，下部接合线被包围在膜间隔离器上并由其保护。 此外，薄膜在线间隔物是薄的，导致堆叠的电子部件封装的最小高度。

公开(公告)号：US08049287B2

公开(公告)日：2011-11-01

申请号：US12102709

申请日：2008-04-14

Applicant: Chantal Combi ,  Benedetto Vigna ,  Federico Giovanni Ziglioli ,  Lorenzo Baldo ,  Manuela Magugliani ,  Ernesto Lasalandra ,  Caterina Riva

Inventor： Chantal Combi ,  Benedetto Vigna ,  Federico Giovanni Ziglioli ,  Lorenzo Baldo ,  Manuela Magugliani ,  Ernesto Lasalandra ,  Caterina Riva

IPC: H01L29/84

CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

Abstract translation: 一种基板级组件，其具有具有顶面的半导体材料的器件基板并且容纳第一集成器件，所述第一集成器件包括形成在所述器件衬底内的掩埋腔，以及悬挂在所述顶面附近的所述掩埋腔上的膜。 封盖衬底在顶面上方连接到器件衬底，以便以这样的方式覆盖第一集成器件，使得在膜上方设置第一空白空间。 电接触元件将集成器件与衬底级组件的外部电连接。 在一个实施例中，器件衬底集成了至少一个设置有相应膜的集成器件，并且在另一个集成器件的相应膜上提供了与第一空白空间流体隔离的另外的空白空间。

公开(公告)号：US07992443B2

公开(公告)日：2011-08-09

申请号：US12644331

申请日：2009-12-22

Applicant: Bernhard Opitz ,  Christian Doering ,  Hans Artmann ,  Janpeter Wolff ,  Remigius Niekrawietz

Inventor： Bernhard Opitz ,  Christian Doering ,  Hans Artmann ,  Janpeter Wolff ,  Remigius Niekrawietz

IPC: G01L9/12

CPC classification number: G01L9/0072 ,  B81B3/0078 ,  B81B2201/0264 ,  G01L13/025

Abstract: A sensor design, respectively a micromechanical sensor structure for capacitive relative-pressure measurement, that will allow very small pressure differentials to be reliably recorded at high absolute pressures even in harsh, particle-laden measuring environments. For that purpose, the micromechanical sensor element includes a deflectable diaphragm structure which is provided with at least one deflectable electrode, and a fixed support structure for at least one fixed counter-electrode which is located opposite the deflectable electrode. The diaphragm structure includes two mutually parallel configured diaphragms that are joined rigidly to one another via at least one connecting crosspiece, so that each application of force to one of the two diaphragms is directly transmitted to the respective other diaphragm. The first diaphragm is able to be pressurized by a first measuring pressure emanating from the front side of the sensor element, and the second diaphragm is able to be pressurized by a second measuring pressure emanating from the rear side of the sensor element. The fixed counter-electrode is located in the sealed volume between the two diaphragms of the diaphragm structure.

Abstract translation: 传感器设计分别是用于电容式相对压力测量的微机械传感器结构，即使在苛刻的，充满颗粒的测量环境中，也能够将极小的压差可靠地记录在高绝对压力下。 为此目的，微机械传感器元件包括可偏转的膜结构，其具有至少一个可偏转电极，以及用于至少一个与可偏转电极相对的固定对置电极的固定支撑结构。 隔膜结构包括通过至少一个连接横档彼此刚性地连接的两个相互平行的构造的隔膜，使得对两个隔膜中的一个的每个施加的力直接传递到相应的另一个隔膜。 第一隔膜能够通过从传感器元件的前侧发出的第一测量压力被加压，并且第二隔膜能够被从传感器元件的后侧发出的第二测量压力加压。 固定对置电极位于隔膜结构的两个隔膜之间的密封体积中。

公开(公告)号：US20110163396A1

公开(公告)日：2011-07-07

申请号：US12737036

申请日：2009-04-21

Applicant: Hubert Benzel ,  Frank Henning ,  Armin Scharping ,  Christoph Schelling

Inventor： Hubert Benzel ,  Frank Henning ,  Armin Scharping ,  Christoph Schelling

IPC: H01L29/84 ,  H01L21/02

CPC classification number: B81C3/001 ,  B81B2201/0264 ,  B81C2201/019 ,  G01L9/0055

Abstract: The present invention relates to a manufacturing method for a micromechanical component, a corresponding composite component, and a corresponding micromechanical component. The method has the following steps: providing a first composite (W1; W1′; W1″; W1′″) of a plurality of semiconductor chips (SC1, SC2, SC3; SC2″; SC1′″, SC2′″; SC3′″), the first composite having a first front surface (V1; V1′; V1″; V1′″) and a first back surface (R1; R1′; R1″; R1′″); providing a second composite (W2; W2′) of a corresponding plurality of carrier substrates (SS1, SS2, SS3; SS1′″, SS2′″, SS3′″), the second composite having a second front surface (V2; V2′″) and a second back surface (R2; R2′″); imprinting a structured adhesion promoter layer (SG) on the first front surface (V1; V1′; V1″; V1′″) and/or the second front surface (V2; V2′″), the layer having degassing channels (SK, KG); aligning the first front surface (V1; V1′; V1″; V1′″) and the second front surface (V2; V2′″) corresponding to a plurality of micromechanical components, each having a semiconductor chip (SC1, SC2, SC3; SC2″; SC1′″, SC2′″; SC3′″) and a corresponding carrier substrate (SS1, SS2, SS3; SS1′″, SS2′″, SS3′″); connecting the first front surface (V1; V1′; V1″; V1′″) and the second front surface (V2; V2′″) via the structured adhesion promoter layer (SG) by applying pressure in such a way that each semiconductor chip (SC1, SC2, SC3; SC2″; SC1′″, SC2′″; SC3′″) is connected to a corresponding carrier substrate (SS1, SS2, SS3; SS1′″, SS2′″, SS3′″) corresponding to a respective micromechanical component, so that a gas from the ambient atmosphere is able to escape to the outside through the degassing channels (SK, KG); and separating the micromechanical components.

公开(公告)号：US20110163395A1

公开(公告)日：2011-07-07

申请号：US12651623

申请日：2010-01-04

Applicant: Thoralf Kautzsch ,  Marco Müller ,  Dirk Meinhold ,  Ben Rosam ,  Klaus Elian ,  Stefan Kolb

Inventor： Thoralf Kautzsch ,  Marco Müller ,  Dirk Meinhold ,  Ben Rosam ,  Klaus Elian ,  Stefan Kolb

IPC: H01L29/84 ,  H01L21/78

CPC classification number: B81C1/00071 ,  B81B2201/0264 ,  G01L9/0042

Abstract: A method for providing a pressure sensor substrate comprises creating a first cavity that extends inside the substrate in a first direction perpendicular to a main surface of the substrate, and that extends inside the substrate, in a second direction perpendicular to the first direction, into a first venting area of the substrate; creating a second cavity that extends in the first direction inside the substrate, that extends in parallel to the first cavity in the second direction, and that does not extend into the first venting area; and opening the first cavity in the first venting area.

Abstract translation: 一种用于提供压力传感器基板的方法包括：在垂直于基板的主表面的第一方向上形成在基板内延伸的第一空腔，并且在垂直于第一方向的第二方向上延伸到基板的内部， 基板的第一通气区域; 形成第二空腔，该第二空腔沿第一方向在基板内延伸，该第二空腔在第二方向上平行于第一空腔延伸，并且不延伸到第一排气区域; 并打开第一个通风区域的第一个空腔。