公开(公告)号：US3725671A

公开(公告)日：1973-04-03

申请号：US3725671D

申请日：1970-11-02

Applicant: US NAVY

Inventor： KEISTER F ,  RUST J

IPC: C06B27/00 ,  C06B43/00 ,  F41H13/00 ,  G06K19/073 ,  H01L23/58 ,  H01L27/02 ,  H05K1/00 ,  C06B19/02 ,  H03K17/84 ,  H05K1/18

CPC classification number: G06K19/07381 ,  C06B27/00 ,  C06B43/00 ,  F41H13/00 ,  G06K19/073 ,  G06K19/07372 ,  H01L23/573 ,  H01L27/02 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/19107 ,  H05K1/0275 ,  H05K1/0293 ,  H05K2201/0317 ,  H05K2203/1163 ,  H05K2203/175 ,  Y10S257/922 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An anticompromise pyrotechnic eradication thin film circuit module having thin films of perfluoropolymer and metal thereon in sufficient quantity to produce a pyrotechnic reaction to cause heat of fusion of the metals of the thin film circuit to destroy the circuit beyond recognition and repair.

Abstract translation: 一种防爆烟火根除薄膜电路模块，其具有足够量的全氟聚合物和金属薄膜，以产生烟火反应，引起薄膜电路的金属熔化热，从而破坏电路，使其不被识别和修复。

公开(公告)号：US3649392A

公开(公告)日：1972-03-14

申请号：US3649392D

申请日：1968-12-06

Applicant: WESTERN ELECTRIC CO

Inventor： SCHNECK JAMES F

IPC: C23F1/02 ,  H01L21/70 ,  H01L49/02 ,  H05K1/16 ,  H05K3/38 ,  H05K1/00 ,  H01L7/50

CPC classification number: H05K1/167 ,  C23F1/02 ,  H01L21/707 ,  H01L49/02 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2203/0361 ,  Y10T29/49156

Abstract: IN THE MANUFACTURE OF THIN-FILM CIRCUITS FROM SUBSTRATES HAVING SUPERIMPOSED FILMS OF A RESISTIVE AND A CONDUCTIVE MATERIAL, THE UNDERCUTTING OF RESISTORS OR THE UNINTENTIONAL REDUCTION OF CONDUCTOR-TERMINATION PAD DIMENSIONS BY MISREGISTRATION IS ELIMINATED THROUGH THE USE OF A FIRST "ROUGH" MASK TO PERMIT REMOVAL OF THE CONDUCTIVE FILM FROM THE GENERAL AREA WHERE THE RESISTORS WILL BE FORMED. A SECOND MASK IN THE CONFIGURATION OF THE ENTIRE THIN-FILM CIRCUIT IS USED TO PERMIT THE REMOVAL OF THE REMAINING UNWANTED PORTIONS OF THE THIN FILMS. SINCE THE RESISTOR PORTION OF THE SECOND MASK FALLS DIRECTLY ON THE RESISTIVE FILM IN THE GENERAL AREA WHTER THE CONDUCTIVE FILM WAS REMOVED BY THE FIRST MASK, AND THE SECOND MASK CONTAINS THE ENTIRE THIN-FILM CIRCUIT, BOTH UNDERCUTTING AND MISREGISTRATION, WHICH LEADS TO UNINTENTIONAL REDUCTION OF CONDUCTOR-TERMINATION PAD DIMENSIONS, ARE AVOIDED.

公开(公告)号：US3647533A

公开(公告)日：1972-03-07

申请号：US3647533D

申请日：1969-08-08

Applicant: US NAVY

Inventor： HICKS ROBERT E

IPC: H01L21/60 ,  H01L25/18 ,  H05K3/14 ,  H05K3/40 ,  B44D1/52

CPC classification number: H01L24/81 ,  H01L25/18 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/19043 ,  H05K3/143 ,  H05K3/4007 ,  H05K2201/0317 ,  H05K2201/0367 ,  Y10S428/901

Abstract: A method for producing reliable bonding bumps on large-scale array substrates and hybrid add-on components, the present invention is compatible with a wide variety of microcircuit components. Generally, the method envisions fabrication of bonding bumps by thin-film vacuum deposition through a mechanical mask. In particular, a first metal is deposited on a substrate to a desired thickness whereupon said first metal is then codeposited with a second metal. The bump is completed with the sole deposition of the second metal. A bump thus produced may be further processed to produce a ''''solder-dipped bump'''' or may be used in the thin-film state for component mounting.

Abstract translation: 一种用于在大规模阵列基板和混合附加部件上制造可靠的接合凸块的方法，本发明与各种微电路部件兼容。 通常，该方法设想通过机械掩模通过薄膜真空沉积制造接合凸块。 特别地，将第一金属沉积在基底上至所需厚度，然后所述第一金属然后用第二金属共沉积。 用第二金属的唯一沉积完成凸块。 可以进一步处理由此产生的凸块以产生“焊料浸渍凸起”，或者可以以薄膜状态用于部件安装。

公开(公告)号：US3634159A

公开(公告)日：1972-01-11

申请号：US3634159D

申请日：1970-06-24

Applicant: DECCA LTD

Inventor： CROSKERY WILLIAM FLETCHER

IPC: H01C17/00 ,  H01L49/02 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/38 ,  C23F1/02

CPC classification number: H05K1/167 ,  H01C17/003 ,  H01L49/02 ,  H05K3/062 ,  H05K3/243 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10S428/901

Abstract: A method of forming a two-dimensional electrical circuit assembly. A substrate is coated with a thin gold layer. The gold layer is removed from marginal areas not associated with the regions of conductive elements and resistive elements of the assembly. The gold layer in the regions of the conductive layers are plated with more gold and the resistive layer in the marginal areas is removed using the gold as a resist. Finally the remaining gold is etched to remove the gold layer from the regions of the resistive elements and to leave gold plating forming the conductive elements.

Abstract translation: 一种形成二维电路组件的方法。 衬底涂有薄金层。 从与组件的导电元件和电阻元件的区域不相关的边缘区域去除金层。 在导电层的区域中的金层被镀更多的金，并且使用金作为抗蚀剂去除边缘区域中的电阻层。 最后，蚀刻剩余的金以从电阻元件的区域去除金层，并且留下形成导电元件的镀金。

公开(公告)号：US3275894A

公开(公告)日：1966-09-27

申请号：US37412964

申请日：1964-06-10

Applicant: INT STANDARD ELECTRIC CORP

Inventor： HANS REINER

IPC: H01G2/00 ,  H01G4/10 ,  H01L27/01 ,  H03K19/02 ,  H05K1/16 ,  H05K3/46

CPC classification number: H01G2/00 ,  H01G4/10 ,  H01L27/016 ,  H03K19/02 ,  H05K1/162 ,  H05K3/4685 ,  H05K2201/0317 ,  H05K2203/0315

公开(公告)号：US3198718A

公开(公告)日：1965-08-03

申请号：US10310461

申请日：1961-04-14

Applicant: LOCKHEED AIRCRAFT CORP

Inventor： QUINN ROSS A

IPC: H01C1/16 ,  H01C7/00 ,  H05K1/16 ,  H05K1/18 ,  H05K3/40

CPC classification number: H01C7/00 ,  H01C1/16 ,  H05K1/167 ,  H05K1/182 ,  H05K3/4046 ,  H05K3/4076 ,  H05K2201/0317 ,  H05K2201/09981 ,  H05K2201/10174 ,  H05K2201/10651 ,  H05K2203/0315

公开(公告)号：US3191098A

公开(公告)日：1965-06-22

申请号：US3194760

申请日：1960-05-26

Applicant: LOCKHEED AIRCRAFT CORP

Inventor： FULLER WILLIAM D

IPC: H05K1/03 ,  H05K1/09 ,  H05K1/16 ,  H05K1/18 ,  H05K3/40 ,  H05K3/42

CPC classification number: H05K1/162 ,  H05K1/0306 ,  H05K1/095 ,  H05K1/182 ,  H05K3/4076 ,  H05K3/42 ,  H05K2201/0317 ,  H05K2201/09809 ,  H05K2203/0315 ,  H05K2203/1142 ,  Y10T29/435

公开(公告)号：US2861911A

公开(公告)日：1958-11-25

申请号：US47611654

申请日：1954-12-20

Applicant: MOLDED FIBER GLASS BODY COMPAN

Inventor： MORGAN MARTIN ,  BOJANOWSKI CLEMENT J

IPC: H05K3/10 ,  H05K3/14 ,  H05K3/20

CPC classification number: H05K3/20 ,  H05K3/107 ,  H05K3/14 ,  H05K3/143 ,  H05K2201/0317 ,  H05K2201/0376 ,  H05K2201/09118 ,  H05K2203/016 ,  H05K2203/0278 ,  H05K2203/0557 ,  H05K2203/104 ,  H05K2203/1344 ,  Y10S264/53 ,  Y10S425/811 ,  Y10T29/4916 ,  Y10T29/49984

公开(公告)号：US2662957A

公开(公告)日：1953-12-15

申请号：US19162950

申请日：1950-10-23

Applicant: PAUL EISLER

Inventor： PAUL EISLER

IPC: H01B1/00 ,  H01C7/04 ,  H05K1/09 ,  H05K1/16 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/07

CPC classification number: H05K1/167 ,  H01B1/00 ,  H01C7/041 ,  H05K1/095 ,  H05K1/162 ,  H05K3/022 ,  H05K3/04 ,  H05K3/06 ,  H05K3/07 ,  H05K2201/0317 ,  H05K2201/0323 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/025 ,  H05K2203/0361 ,  H05K2203/0723 ,  Y10S428/901 ,  Y10S428/931 ,  Y10S438/98 ,  Y10T29/49099 ,  Y10T29/49156 ,  Y10T428/12361 ,  Y10T428/12451 ,  Y10T428/12486 ,  Y10T428/12507 ,  Y10T428/12528 ,  Y10T428/12535 ,  Y10T428/12986

公开(公告)号：US20240284591A1

公开(公告)日：2024-08-22

申请号：US18650918

申请日：2024-04-30

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Tsuyoshi TAKAKURA ,  Masaaki MIZUSHIRO ,  Satoshi IZUMI ,  Ryuichiro WADA ,  Hiroki YOSHIMORI ,  Yoshihito OTSUBO ,  Tadashi NOMURA

IPC: H05K1/02

CPC classification number: H05K1/0271 ,  H05K2201/0317 ,  H05K2201/0338 ,  H05K2201/0367 ,  H05K2201/0391

Abstract: A circuit module includes: a substrate including a first main surface and a second main surface; a resin layer on the first main surface of the substrate; an electronic component; a penetrating portion penetrating the resin layer in a thickness direction; a first conductor that is a pillar conductor present in the penetrating portion, the first conductor including a first bottom closer to the substrate and a second bottom inward of an outer surface of the resin layer; a second conductor that is a metal film covering at least a portion of a side surface of the first conductor, the second conductor including a portion extending continuously from the side surface of the first conductor to the same plane with the outer surface of the resin layer.