公开(公告)号：US20050237776A1

公开(公告)日：2005-10-27

申请号：US11089567

申请日：2004-03-19

Applicant: Adrian Gropper ,  Sean Doyle ,  William Donner ,  Hugh Cottingham

Inventor： Adrian Gropper ,  Sean Doyle ,  William Donner ,  Hugh Cottingham

IPC: G06F17/00 ,  G06F17/50 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00

CPC classification number: G06F17/5036 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09236

Abstract: A method for verifying coupling in a differential via pair group includes identifying a differential via pair group in a design database and identifying a victim differential via pair in the differential via pair group. All other differential via pairs in the differential via pair group are identified as culprit differential pairs. The differential via pair group includes at least one culprit differential via pair. The method also includes obtaining a total coupling threshold level and calculating a total coupling factor for the victim differential via pair within the differential via pair group. The method also includes flagging the victim differential via pair if the calculated total coupling factor exceeds the total coupling threshold level.

Abstract translation: 用于验证差分通路对组合中的耦合的方法包括在设计数据库中识别差分通路对组，并且通过差分通路对组中的对识别受害者差分。 差分通孔对组中的所有其他差分通孔对被识别为凶手差分对。 差分通路对组包括至少一个故障差分通路对。 该方法还包括获得总耦合阈值电平并且计算差分通路对组内的受损差分通路对的总耦合因子。 如果计算的总耦合系数超过总耦合阈值电平，该方法还包括通过对标记受害者差分。

公开(公告)号：US20050201072A1

公开(公告)日：2005-09-15

申请号：US10797753

申请日：2004-03-09

Applicant: Jiangqi He ,  Joong-ho Kim ,  Hyunjun Kim ,  Dong-ho Han ,  Ping Sun

Inventor： Jiangqi He ,  Joong-ho Kim ,  Hyunjun Kim ,  Dong-ho Han ,  Ping Sun

IPC: H01P3/08 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H01P3/085 ,  H01P3/081 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09727

Abstract: An apparatus comprises a signal layer including a first and second signal trace. The apparatus also comprises a first reference plane including a first slot substantially parallel to the first and second signal traces. Further, the apparatus includes a dielectric layer having at least a portion disposed between the signal layer and the first reference plane.

Abstract translation: 一种装置包括包括第一和第二信号迹线的信号层。 该装置还包括第一参考平面，该第一参考平面包括基本上平行于第一和第二信号迹线的第一槽。 此外，该装置包括具有设置在信号层和第一参考平面之间的至少一部分的电介质层。

公开(公告)号：US20050190631A1

公开(公告)日：2005-09-01

申请号：US11089521

申请日：2005-03-24

Applicant: Dean Klein

Inventor： Dean Klein

IPC: G06F13/40 ,  G11C7/10 ,  G11C8/00 ,  H05K1/18

CPC classification number: G11C7/1048 ,  G06F13/4077 ,  G11C2207/002 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/10053 ,  H05K2201/10159 ,  Y02P70/611

Abstract: Data bus capacitance is reduced by decoupling unaccessed memory circuits from a data bus during data transfers to or from other memory circuits.

公开(公告)号：US20050156319A1

公开(公告)日：2005-07-21

申请号：US10515511

申请日：2003-04-18

Applicant: Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

Inventor： Stefano Oggioni ,  Michele Castriotta ,  Gianluca Rogiani ,  Mauro Spreafico ,  Giorgio Viero

IPC: H05K3/46 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H01L23/48

CPC classification number: H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/115 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/09381 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/0979 ,  H01L2924/00

Abstract: A stacked via structure (200) adapted to transmit high frequency signals or high intensity current through conductive layers of an electronic device carrier is disclosed. The stacked via structure comprises at least three conductive tracks (205a, 205b, 205c) belonging to three adjacent conductive layers (110a, 110b, 110c) separated by dielectric layers (120), aligned according to z axis. Connections between these conductive tracks are done with at least two vias (210, 215) between each conductive layer. Vias connected to one side of a conductive track are disposed such that they are not aligned with the ones connected to the other side according to z axis. In a preferred embodiment, the shape of these aligned conductive tracks looks like a disk or an annular ring and four vias are used to connect two adjacent conductive layers. These four vias are symmetrically disposed on each of said conductive track. The position of the vias between a first and a second adjacent conductive layers and between a second and a third adjacent conductive layers forms an angle of 45° according to z axis.

Abstract translation: 公开了一种适于通过电子设备载体的导电层传输高频信号或高强度电流的堆叠通孔结构（200）。 叠置的通孔结构包括属于由电介质层（120）分开的根据z轴对准的三个相邻导电层（110a，110b，110c）的至少三个导电轨道（205a，205b，205c）。 这些导电轨道之间的连接通过在每个导电层之间的至少两个通孔（210,215）进行。 连接到导电轨道的一侧的通孔布置成使得它们不与根据z轴连接到另一侧的那些对准。 在优选实施例中，这些对准的导电轨迹的形状看起来像盘或环形环，并且四个通孔用于连接两个相邻的导电层。 这四个通孔对称地设置在每个导电轨道上。 在第一和第二相邻导电层之间以及第二和第三相邻导电层之间的通孔的位置根据z轴形成45°的角度。

公开(公告)号：US06914500B2

公开(公告)日：2005-07-05

申请号：US10468874

申请日：2002-12-12

Applicant: Takayuki Hirabayashi

Inventor： Takayuki Hirabayashi

IPC: H05K3/46 ,  H01P1/203 ,  H01P3/08 ,  H01P7/08 ,  H05K1/16 ,  H05K3/02

CPC classification number: H01P1/20345 ,  H01L2224/16225 ,  H01L2924/15184 ,  H01L2924/16152 ,  H01P1/203 ,  H05K1/16 ,  H05K3/02 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/09236 ,  H05K2201/1006

Abstract: This invention is a filter circuit having a filter element. A filter element (4) is a parallel resonator circuit including a pair of first resonator lines (19a) (19b) formed by a thick film forming technique and a pair of second resonator lines (20a) (20b). As the thickness of the pair of second resonator lines (20a) (20b) is significantly reduced, the impedance ratio between the pair of second resonator lines (20a) (20b) and the pair of first resonator lines (19a) (19b) is increased. Therefore, the length of these pairs of resonator lines (19a) (19b) (20a) (20b) is reduced and miniaturization of the filter element is realized.

Abstract translation: 本发明是一种具有滤光元件的滤光电路。 滤波器元件（4）是包括通过厚膜形成技术形成的一对第一谐振器线（19a）和一对第二谐振器线（20b）的并联谐振器电路。 当一对第二谐振器线路（20a）（20b）的厚度大大减小时，一对第二谐振器线路（20b）和第一谐振器线路（20A）之间的阻抗比 ）（19b）增加。 因此，这些谐振器线对（20a）（20b）（20b）（20a）（20b）的长度被减小并且实现了滤波器元件的小型化。

公开(公告)号：US20050140462A1

公开(公告)日：2005-06-30

申请号：US11063132

申请日：2005-02-22

Applicant: Salman Akram ,  Kie Ahn ,  Leonard Forbes

Inventor： Salman Akram ,  Kie Ahn ,  Leonard Forbes

IPC: H01L23/522 ,  H01L23/552 ,  H05K1/02 ,  H01P3/08 ,  H01P1/26 ,  H01P5/02

CPC classification number: H01L23/5225 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0219 ,  H05K1/0233 ,  H05K2201/083 ,  H05K2201/09236 ,  H01L2924/00

Abstract: A structure for magnetically shielded transmission lines for use with high speed integrated circuits having an improved signal to noise ratio, and a method for forming the same are disclosed. At least one magnetic shield structure contains electrically induced magnetic fields generated around a number of transmission lines. The shield material is made of alternating layers of magnetic material and insulating material.

Abstract translation: 公开了一种用于具有改善的信噪比的高速集成电路的用于磁屏蔽传输线的结构及其形成方法。 至少一个磁屏蔽结构包含围绕多个传输线产生的电感应磁场。 屏蔽材料由交替的磁性材料层和绝缘材料制成。

公开(公告)号：US20050139391A1

公开(公告)日：2005-06-30

申请号：US10977192

申请日：2004-10-29

Applicant: Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

Inventor： Yuan-Liang Li ,  Jiangqi He ,  Dong Zhong ,  David Figueroa

IPC: H01L23/498 ,  H01L23/66 ,  H01P3/08 ,  H05K1/02 ,  H05K7/06

CPC classification number: H01P3/081 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H05K1/0242 ,  H05K1/0245 ,  H05K1/0265 ,  H05K3/4644 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0979 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: Trace configurations for carrying high-speed digital differential signals provide for reduced conduction loss and improved signal integrity. In one embodiment, a circuit board has a first set of conductive traces disposed on non-conductive material, and a second set of conductive traces parallel to the first set and disposed within the conductive material. The second set is separated from the first set by non-conductive material. Corresponding traces of the first and second sets may be in a stacked configuration. In other embodiments, conductive material may be provided between corresponding traces of the first and second sets resulting in an “I-shaped” or “U-shaped” cross-section. In yet other embodiments, the trace configurations have “T-shaped” and “L-shaped” cross-sections.

公开(公告)号：US06898844B2

公开(公告)日：2005-05-31

申请号：US09964810

申请日：2001-09-28

Applicant: Christopher N. Olsen

Inventor： Christopher N. Olsen

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/42 ,  H01R43/00

CPC classification number: H05K1/0216 ,  H05K3/0005 ,  H05K3/429 ,  H05K2201/09236 ,  Y10T29/49004 ,  Y10T29/49117 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method is provided for designing a printed circuit board. This may include analyzing at least one characteristic of a first plurality of relatively parallel conductive paths on the printed circuit board. The first plurality of relatively parallel conductive paths may be arranged in a pattern in a first area of the printed circuit board. The method may also include rearranging the pattern of conductive paths such that a second plurality of relatively parallel conductive paths in a second area of the printed circuit board have a different geometry or arrangement with respect to one another as compared to a geometry or arrangement of the first plurality of relatively parallel conductive paths in the first area.

Abstract translation: 提供了一种用于设计印刷电路板的方法。 这可以包括分析印刷电路板上的第一多个相对平行的导电路径的至少一个特性。 第一多个相对平行的导电路径可以布置在印刷电路板的第一区域中的图案中。 该方法还可以包括重新布置导电路径的图案，使得印刷电路板的第二区域中的第二多个相对平行的导电路径相对于彼此具有不同的几何形状或布置，与 在第一区域中的第一多个相对平行的导电路径。

公开(公告)号：US20050092513A1

公开(公告)日：2005-05-05

申请号：US11001445

申请日：2004-11-30

Applicant: David Brunker ,  Daniel Dawiedczyk ,  John Lopata ,  Arindum Dutta

Inventor： David Brunker ,  Daniel Dawiedczyk ,  John Lopata ,  Arindum Dutta

IPC: H01B11/00 ,  H01P1/02 ,  H01P3/02 ,  H01R9/03 ,  H01R12/50 ,  H01R12/71 ,  H01R12/79 ,  H01R13/648 ,  H05K1/00 ,  H05K1/02 ,  H05K1/14 ,  H05K3/10 ,  H05K3/40 ,  H01B9/02

CPC classification number: H05K1/024 ,  H01P3/02 ,  H01R12/716 ,  H01R12/79 ,  H01R13/658 ,  H05K1/0284 ,  H05K1/145 ,  H05K3/107 ,  H05K3/403 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/09236 ,  H05K2201/09645 ,  H05K2201/09981 ,  H05K2201/10189 ,  H05K2201/10893

Abstract: Termination assemblies for terminating high-frequency data signal transmission lines include housings with one or more cavities that receive ends of the transmission line therein. The transmission line typically includes a dielectric body and a plurality of conductive elements disposed thereon, with the plurality of conductive elements being arranged in pairs for differential signal transmission. The termination assemblies, in one embodiment include hollow end caps that are formed from a dielectric and which have one or more conductive contacts or plated surfaces disposed on or within the cavity so that they will frictionally mate with the conductive traces on the transmission line. In another embodiment, a connector housing is provided with a center slot and a plurality of dual loop contacts to provide redundant circuit paths and low inductance to the termination assembly. A coupling element may be utilized in the slot to achieve a desired level of coupling between the termination contacts.

Abstract translation: 用于终止高频数据信号传输线路的终端组件包括具有一个或多个腔体的壳体，该腔体容纳传输线路的端部。 传输线通常包括绝缘体和设置在其上的多个导电元件，多个导电元件成对布置以用于差分信号传输。 终端组件在一个实施例中包括由电介质形成并且具有一个或多个导电触点或设置在空腔中或腔内的电镀表面的空心端盖，使得它们将与传输线上的导电迹线摩擦配合。 在另一个实施例中，连接器壳体设置有中心狭槽和多个双环触点，以向终端组件提供冗余电路路径和低电感。 可以在槽中使用耦合元件以实现端接触点之间期望的耦合水平。

公开(公告)号：US20050067187A1

公开(公告)日：2005-03-31

申请号：US10957178

申请日：2004-09-30

Applicant: Shou-Kuo Hsu

Inventor： Shou-Kuo Hsu

IPC: H05K1/02 ,  H05K3/40 ,  H05K7/06

CPC classification number: H05K1/0228 ,  H05K1/0237 ,  H05K2201/09236 ,  H05K2201/09672

Abstract: A printed circuit board and a routing scenario thereof are disclosed. The printed circuit board includes three dielectric layers, two signal layers and several differential pairs. Some differential pairs are disposed in one signal layer, while some differential pairs are interleavingly disposed in the adjacent other signal layer. The differential pairs in one signal layer carries signals that flows to one direction, while the differential pairs in the adjacent signal layer carries signals that flows to an opposite direction. Under such a routing scenario, the crosstalk between differential pairs in adjacent signal layers may be reduced.

Abstract translation: 公开了一种印刷电路板及其路由场景。 印刷电路板包括三个电介质层，两个信号层和几个差分对。 一些差分对设置在一个信号层中，而一些差分对被交织地布置在相邻的其它信号层中。 一个信号层中的差分对携带流向一个方向的信号，而相邻信号层中的差分对携带流向相反方向的信号。 在这种路由情况下，可以减少相邻信号层中的差分对之间的串扰。