公开(公告)号：US20050237364A1

公开(公告)日：2005-10-27

申请号：US11113459

申请日：2005-04-25

Applicant: Hirosumi Ito

Inventor： Hirosumi Ito

IPC: B41J2/045 ,  B41J2/05 ,  B41J2/055 ,  B41J2/14 ,  B41J29/00 ,  H05K3/00 ,  H05K3/32 ,  H05K3/36 ,  H05K3/40

CPC classification number: H05K3/4007 ,  B41J2/14209 ,  B41J2002/14217 ,  B41J2002/14225 ,  B41J2002/14306 ,  B41J2002/14459 ,  B41J2002/14491 ,  H05K3/0058 ,  H05K3/321 ,  H05K3/361 ,  H05K3/365 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/091 ,  H05K2201/10977 ,  H05K2203/0195

Abstract: There is disclosed a printed wiring board comprising: an electrically insulating flexible layer which has on one of its opposite sides a protrusion which forms a corresponding recess on the other side of the flexible layer; an electrically conducting layer formed on the protrusion; and a wire formed on the flexible layer, connected to the conducting layer, and extending in a direction. The conducting layer has a shape long in the direction of extension of the wire.

Abstract translation: 公开了一种印刷电路板，包括：电绝缘柔性层，其在其相对侧的一侧上具有在柔性层的另一侧上形成相应凹部的突起; 形成在所述突起上的导电层; 以及形成在柔性层上的导线，连接到导电层并沿一个方向延伸。 导电层具有沿导线延伸方向长的形状。

公开(公告)号：US20050237077A1

公开(公告)日：2005-10-27

申请号：US11171153

申请日：2005-06-30

Applicant: Alan Wood ,  Tim Corbett

Inventor： Alan Wood ,  Tim Corbett

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/26 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L23/13 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract translation: 一个可重复使用的老化/测试夹具，用于测试由半个半部组成的半导体晶圆上的无引脚骰子。 测试夹具的前半部分是用于接收晶片的晶片腔板，第二半部分在晶片和电气测试设备之间建立电气连通。 刚性基板在其上具有与晶片电接触的导体。 在老化和电气测试完成之前，测试夹具不需要打开。 在老化应力和电气测试之后，可以将单个裸片或单独的封装裸片与封装裸片之间建立互为独立部件，阵列或簇的互连，或者作为单个部分或阵列。

公开(公告)号：US06949412B2

公开(公告)日：2005-09-27

申请号：US10410256

申请日：2003-04-10

Applicant: Kinji Saijo ,  Kazuo Yoshida ,  Hiroaki Okamoto ,  Shinji Ohsawa

Inventor： Kinji Saijo ,  Kazuo Yoshida ,  Hiroaki Okamoto ,  Shinji Ohsawa

IPC: H01L23/31 ,  H01L23/495 ,  H01L23/498 ,  H05K3/06 ,  H05K3/28 ,  H05K3/40 ,  H01L21/50 ,  B21D33/00 ,  H01S4/00

CPC classification number: H01L23/3114 ,  H01L23/3107 ,  H01L23/49582 ,  H01L23/49861 ,  H01L2224/16 ,  H01L2924/07811 ,  H05K3/062 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2203/0384 ,  H05K2203/1572 ,  Y10T29/30 ,  Y10T29/301 ,  Y10T29/302 ,  Y10T29/49002 ,  Y10T428/1291 ,  H01L2924/00

Abstract: A clad plate for forming an interposer for a semiconductor device which can be manufactured at low cost and has good characteristics, an interposer for a semiconductor device, and a method of manufacturing them. Copper foil materials (19, 24, 33) forming conductive layers (10, 17, 18) and nickel plating (20, 21) forming etching stopper layers (11, 12) are formed and pressed to form a clad plate (34) for forming an interposer for a semiconductor device. Thus, a clad plate (34) for forming an interposer for a semiconductor device is manufactured. The clad plate (34) is selectively etched to form a columnar conductor (17), and an insulating layer (13) is formed on the copper foil material forming a wiring layer (10). A bump (18) for connection of a semiconductor chip and the wiring layer (10) are formed on the opposite side to the side on which the columnar conductor (17) is formed. Thus, an interposer for a semiconductor device is manufactured.

Abstract translation: 一种用于形成可以低成本且具有良好特性的半导体器件的插入件的复合板，用于半导体器件的插入件及其制造方法。 形成形成蚀刻停止层（11,12）的导电层（10,17,18）和镀镍（20,21）的铜箔材料（19,24,33）并被压制以形成用于 形成用于半导体器件的插入件。 因此，制造用于形成用于半导体器件的插入件的复合板（34）。 选择性地蚀刻包覆板（34）以形成柱状导体（17），并且在形成布线层（10）的铜箔材料上形成绝缘层（13）。 用于连接半导体芯片和布线层（10）的凸起（18）形成在与形成柱状导体（17）的一侧相反的一侧。 因此，制造了用于半导体器件的插入件。

公开(公告)号：US20050167829A1

公开(公告)日：2005-08-04

申请号：US10791966

申请日：2004-03-03

Applicant: Dennis Brunner ,  David Buster ,  Michael Graff ,  Daniel Luebbert ,  Nathan Kreutter ,  Rui Yang ,  Guoping Mao

Inventor： Dennis Brunner ,  David Buster ,  Michael Graff ,  Daniel Luebbert ,  Nathan Kreutter ,  Rui Yang ,  Guoping Mao

IPC: H01L21/48 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40

CPC classification number: H01L24/10 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/4985 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01061 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01093 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/002 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09036 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2203/0369 ,  H01L2924/00

Abstract: Provided are partially etched dielectric films with raised conductive features. Also provided are methods for forming the raised conductive features in the dielectric films, which methods include partially etching the dielectric films.

Abstract translation: 提供了具有凸起导电特征的部分蚀刻的电介质膜。 还提供了用于在介电膜中形成凸起的导电特征的方法，该方法包括部分蚀刻介电膜。

公开(公告)号：US20050127508A1

公开(公告)日：2005-06-16

申请号：US10897124

申请日：2004-07-23

Applicant: In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

Inventor： In-Young Lee ,  Gu-Sung Kim ,  Se-Young Jeong ,  Sun-Young Park

IPC: H01L23/52 ,  H01L21/60 ,  H01L23/485 ,  H05K3/34 ,  H01L21/44 ,  H01L29/40

CPC classification number: H01L24/13 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05671 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/13613 ,  H01L2224/13616 ,  H01L2224/13639 ,  H01L2224/13644 ,  H01L2224/13647 ,  H01L2224/13655 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2203/0465 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A solder bump structure may have a metal stud formed on a chip pad of a semiconductor chip. Surfaces of the metal stud may be plated with a solder. The metal stud may be located on a substrate pad of the substrate. The substrate pad may have a pre-solder applied thereto. After a solder reflow, the solder bump may have a concave shape.

Abstract translation: 焊料凸块结构可以具有形成在半导体芯片的芯片焊盘上的金属螺柱。 金属螺柱的表面可以镀有焊料。 金属螺柱可以位于衬底的衬底焊盘上。 衬底垫可以具有施加到其上的预焊料。 在焊料回流之后，焊料凸点可以具有凹形。

公开(公告)号：US06891314B2

公开(公告)日：2005-05-10

申请号：US10224577

申请日：2002-08-21

Applicant: Junya Sato ,  Yasuhiro Sasaki

Inventor： Junya Sato ,  Yasuhiro Sasaki

IPC: B41J2/045 ,  B41J2/055 ,  B41J2/135 ,  B41J2/14 ,  B41J2/16 ,  H01L21/60 ,  H01L27/20 ,  H01L41/09 ,  H01L41/22 ,  H01L41/29 ,  H05K3/32 ,  H05K3/36 ,  H01L41/08

CPC classification number: H01L27/20 ,  B41J2002/14459 ,  B41J2002/14491 ,  H01L2224/48091 ,  H05K3/321 ,  H05K3/361 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/10234 ,  H01L2924/00014

Abstract: A common electrode and a signal electrode are separately formed on two major faces of each of tabular piezoelectric actuator elements arrayed on a substrate. On a flexible printed circuit board, formed are electric bonding pads, which are to be electrically connected with the substrate of the actuator elements. A semi-spherical bump including a conductive core and a conductive sealant is formed on each of pads. The actuator elements having substrate is made to face the flexible printed circuit board, and heated under pressure to thereby electrically bond the signal electrodes (at their electric bonding area) to the corresponding bumps. Thus bonded, there exists a gap around the core, and it allows the actuator area of the signal electrode to act completely free, not interfered with any other.

Abstract translation: 公共电极和信号电极分别形成在排列在基板上的每个平板状压电致动器元件的两个主表面上。 在柔性印刷电路板上形成有电连接焊盘，其将与致动器元件的基板电连接。 在每个焊盘上形成包括导电芯和导电密封剂的半球形凸块。 将具有基板的致动器元件制成面对柔性印刷电路板，并在加压下加热，从而将信号电极（在其电接合区域）电连接到相应的凸块。 因此，在芯部周围存在间隙，并且使信号电极的致动器区域能够完全自由地起作用，而不会干扰任何其它的。

公开(公告)号：US06889429B2

公开(公告)日：2005-05-10

申请号：US09817330

申请日：2001-03-26

Applicant: Phillip C. Celaya ,  James S. Donley ,  Stephen C. St. Germain

Inventor： Phillip C. Celaya ,  James S. Donley ,  Stephen C. St. Germain

IPC: H01L23/14 ,  H01L23/498 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/243 ,  H01L23/145 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/8547 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15312 ,  H01L2924/181 ,  H05K3/3436 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2203/0574 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49169 ,  Y10T29/49171 ,  Y10T29/49172 ,  Y10T29/53204 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An integrated circuit package (60) has a substrate (12) with a first surface (51) for mounting a semiconductor die (20) and a second surface (52) defining a via (70). A lead (26) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die.

Abstract translation: 集成电路封装（60）具有基板（12），其具有用于安装半导体管芯（20）的第一表面（51）和限定通孔（70）的第二表面（52）。 通过电镀导电材料从第二表面向外突出而形成引线（26）。 导电材料从引线延伸穿过第一通孔以耦合到半导体管芯。

公开(公告)号：US06880244B2

公开(公告)日：2005-04-19

申请号：US09754133

申请日：2001-01-05

Applicant: Yuji Yagi ,  Takeo Yasuho

Inventor： Yuji Yagi ,  Takeo Yasuho

IPC: H05K1/18 ,  H01L21/48 ,  H01L21/60 ,  H01L23/12 ,  H01L23/498 ,  H05K1/09 ,  H05K3/20 ,  H05K3/22 ,  H05K3/32 ,  H05K3/34 ,  H05K3/40 ,  H05K3/46 ,  H01K3/22

CPC classification number: H05K3/4647 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/092 ,  H05K1/095 ,  H05K3/207 ,  H05K3/22 ,  H05K3/323 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4061 ,  H05K3/4069 ,  H05K3/4664 ,  H05K2201/035 ,  H05K2201/0367 ,  H05K2203/0113 ,  H05K2203/025 ,  H05K2203/0307 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49163 ,  H01L2924/00 ,  H01L2924/00014

Abstract: Method of manufacturing a circuit board and semiconductor device wherein the circuit board has a plurality of wiring patterns and protrusions located on the wiring patterns, the method including simultaneously and unitarily forming the wiring patterns and protrusions, and alternatively coupling electrically the protrusions with electrodes on a semiconductor chip component when present.

Abstract translation: 制造电路板和半导体器件的方法，其中电路板具有位于布线图案上的多个布线图案和突起，该方法包括同时并且整体地形成布线图案和突起，以及将突起与电极电连接 半导体芯片组件存在时。

公开(公告)号：US20050064627A1

公开(公告)日：2005-03-24

申请号：US10901750

申请日：2004-07-29

Applicant: Yuji Kimura ,  Takenobu Maeda ,  Toru Yabe

Inventor： Yuji Kimura ,  Takenobu Maeda ,  Toru Yabe

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/544 ,  H05K1/02 ,  H05K3/30 ,  H05K3/40 ,  H01L21/44 ,  H01L21/48

CPC classification number: H05K1/0269 ,  H01L23/544 ,  H01L24/11 ,  H01L2223/54473 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/1134 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/15787 ,  H05K3/303 ,  H05K3/4015 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/166 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A circuit element having electrodes on one main surface thereof and a substrate having connection bump electrodes and recognition bump electrodes provided on one main surface thereof are prepared. Connection bumps and recognition bumps are formed on the connection bump electrodes and the recognition bump electrodes by using a wire bonding method. Based on the images of the recognition bumps picked up by an optical device, the location of the recognition bumps is detected and, based on the detected location, the circuit element is connected to the substrate through the connection bumps. Since the upper portions of the recognition bumps are in a convex shape, a contrast with respect to the recognition bump electrodes is easily obtained and the location of the recognition bumps can be correctly detected.

Abstract translation: 制备在其一个主表面上具有电极的电路元件和设置在其一个主表面上的具有连接凸块电极和识别凸块电极的基板。 通过使用引线接合方法，在连接凸块电极和识别凸块电极上形成连接凸起和识别凸块。 基于由光学装置拾取的识别凸块的图像，检测识别凸块的位置，并且基于检测到的位置，电路元件通过连接凸块连接到基板。 由于识别凸块的上部是凸形的，因此容易获得相对于识别凸块电极的对比度，并且可以正确地检测识别凸块的位置。

公开(公告)号：US20050046431A1

公开(公告)日：2005-03-03

申请号：US10653766

申请日：2003-09-03

Applicant: Kyle Kirby

Inventor： Kyle Kirby

IPC: G01R3/00 ,  G01R31/28 ,  H05K3/32 ,  H05K3/40 ,  H05K3/42 ,  G01R31/02

CPC classification number: G01R31/2886 ,  G01R3/00 ,  H01L2924/15184 ,  H05K3/326 ,  H05K3/4007 ,  H05K3/4092 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/0969 ,  Y10T29/49002 ,  Y10T29/49004 ,  Y10T29/49126

Abstract: The present disclosure provides probe cards which may be used for testing microelectronic components, including methods of making and using such probe cards. One exemplary implementation provides a probe card that employs a substrate with a plurality of openings. A first probe, which may be used to contact a microelectronic component, includes a first conductor slidably received in one of the openings and a first electrical trace. The electrical trace may be patterned from a metal layer on the back of the substrate and include a resilient free length adapted to urge the first conductor to extend outwardly beyond the front of the substrate. A second probe includes a second conductor slidably received in another one of the openings and a second electrical trace. The second electrical trace may be patterned from a metal layer on the front of the substrate and include a resilient free length adapted to urge the second conductor to extend outwardly beyond the back of the substrate. An electrical pathway through the substrate may electrically couple and first and second electrical traces.

Abstract translation: 本公开提供了可用于测试微电子部件的探针卡，包括制造和使用这种探针卡的方法。 一个示例性实施例提供了采用具有多个开口的基板的探针卡。 可用于接触微电子部件的第一探针包括可滑动地容纳在一个开口中的第一导体和第一电迹线。 电迹线可以从衬底的背面上的金属层图案化，并且包括适于促使第一导体向外延伸超出衬底前部的弹性自由长度。 第二探针包括可滑动地容纳在另一个开口中的第二导体和第二电迹线。 第二电迹线可以从衬底前面的金属层图案化，并且包括适于促使第二导体向外延伸超过衬底背面的弹性自由长度。 穿过衬底的电路可以电耦合和第一和第二电迹线。