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公开(公告)号：US20250112565A1
公开(公告)日：2025-04-03
申请号：US18375005
申请日：2023-09-29
Applicant: STMicroelectronics International N.V.
Inventor： Harsha ADEMANE , Rosario ATTANASIO , Dino COSTANZO
Abstract: Systems, apparatuses, and methods to perform startup step detection in an internal permanent magnet synchronous machine are provided. Startup step detection may providing a motor comprising a rotor and stator, wherein the rotor may be positioned in one of six rotor step positions. The startup step detection may include determining which of the six rotor step positions the rotor is in. This may be performed by determining, prior to starting the motor, a sequence of voltage signals while taking current measurements for each voltage signal. The current measurements may be a change in current over time. Of the current measurements a largest maximum current measurement may be determined, which may be used to identify the current rotor step position.
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22.发明申请公开(公告)号：US20250112556A1
公开(公告)日：2025-04-03
申请号：US18904313
申请日：2024-10-02
Applicant: STMicroelectronics International N.V.
Inventor： Alessandro BERTOLINI , Alessandro GASPARINI
Abstract: A non-inverting buck boost DC-DC converter operates with a ripple-hysteretic-current-mode-control including: a first state where control signals close a first high side switch and a second low side switch; a second state where control signals close the first high side switch and a second high side switch; a third state where control signals close a first low side switch and the second high side switch; and a fourth state where control signals close the first low side switch and the second low side switch. Control signal peak voltage and valley voltage are detected. Passing between the first, second, third and fourth states is dependent on peak voltage detection, valley voltage detection, expiration of a variable first time interval following entering the second state, and expiration of a fixed second time interval following entering the third state.
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公开(公告)号：US20250112107A1
公开(公告)日：2025-04-03
申请号：US18890514
申请日：2024-09-19
Applicant: STMicroelectronics International N.V.
Inventor： Roseanne DUCA
IPC: H01L23/367 , H01L21/48
Abstract: At least one package includes a die including a first surface, a second surface opposite to the first surface, and one or more sidewalls transverse to the first surface and the second surface. The one or more sidewalls extend from the first surface to the second surface. A plurality of separate and distinct heat sinks is on the first surface of the die. Each respective separate and distinct heat sink of the plurality of separate and distinct heat sinks is separate and distinct from adjacent separate and distinct heat sinks of the plurality of separate and distinct heat sinks. A plurality of channels separates each respective heat sink of the plurality of heat sinks from adjacent heat sinks of the plurality of heat sinks. In some packages, an elastic thermally conductive material is present within and fills the plurality of channels.
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公开(公告)号：US12267190B2
公开(公告)日：2025-04-01
申请号：US18644590
申请日：2024-04-24
Applicant: STMicroelectronics International N.V.
Inventor： Iztok Bratuz , Vinko Kunc , Maksimiljan Stiglic
IPC: H04L25/49
Abstract: Various embodiments of the present disclosure disclose decoding techniques for mitigating data corruption due to duty cycle distortion, jitter, and other distortions to a digital signal. Decoding processes, apparatuses, and systems are provided that utilize a decoding framework for improving the accuracy of output bit streams generated from digital signals. An example process receives data indicative of a digital signal, generates a signal measurement for the digital signal that includes signal length descriptive between a two rising edges of a digital signal or two falling edges of the demodulated digital signal, and generates at least one portion of an output bit stream for the digital signal based at least in part on the signal measurement.
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公开(公告)号：US12265124B1
公开(公告)日：2025-04-01
申请号：US18474511
申请日：2023-09-26
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep Jain , Akshay Kumar Jain , Jeena Mary George
IPC: G01R31/319 , G01R31/317 , G01R31/3193
Abstract: According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N−1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N−1 number of redundant flip-flops is observed through the functional path to determine faults.
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Patent Agency Ranking
公开(公告)号：US20250102593A1
公开(公告)日：2025-03-27
申请号：US18472684
申请日：2023-09-22
Applicant: STMicroelectronics International N.V.
Inventor： Francesco Rundo , Michele Calabretta , Marco Maria Branciforte , Concetto Spampinato , Salvatore Coffa
Abstract: A method of characterizing a parameter (e.g., threshold voltage) of a power electronic device using an artificial intelligence (AI) model includes sampling measured parameter values (e.g., voltage, current) of the power electronic device during operation and characterizing the parameter of the power electronic device using the AI model in inference mode with the measured parameter values as inputs. The AI model is trained using a joint loss function including a Jacobian regularization term. The Jacobian regularization term may depend on the norm of at least one Jacobian of a corresponding set of training inputs. A power electronics system configured to perform the method includes the power electronic device and a computing system with a processor and memory storing the AI model. The computing system may be a microcontroller. The system may also include an analog-to-digital converter (ADC) circuit, such as in the microcontroller.
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27.发明申请公开(公告)号：US20250095731A1
公开(公告)日：2025-03-20
申请号：US18824446
申请日：2024-09-04
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Antonino CONTE , Francesco TOMAIUOLO , Jeremie Clement JASSE , Anna GANDOLFO
IPC: G11C13/00
Abstract: A method of operating phase change memories and corresponding device and computer program product are provided. An example of write operations in a phase change memory includes: if a first set contains at least one cell set at a high logic level, performing a reset write operation to set to a low logic level the cell by applying at least one current reset pulse; and if a second set contains at least one cell set at a low logic level, performing a set write operation to set to a high logic level the afore the cell. Success or failure of the set write operation is verified. Success or failure of the reset write operation is verified. The write operation is considered as failed in response to the reset write operation being considered as failed or to the set write operation being considered as failed.
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公开(公告)号：US20250088104A1
公开(公告)日：2025-03-13
申请号：US18463753
申请日：2023-09-08
Applicant: STMicroelectronics International N.V.
Inventor： Sandro Rossi , Niccolò Brambilla , Francesco Franco
Abstract: A Buck converter includes: a first power switch coupled between a supply voltage node and a switching node, where the first power switch is configure to be controlled by a first control signal; a boot-strap capacitor, where a first terminal of the boot-strap capacitor is coupled to the switching node; a first buffer coupled between a first node and a control terminal of the first power switch; a first switch circuit coupled between the first node and a second terminal of the boot-strap capacitor, where the first switch circuit is controlled by the first control signal, and is configured to pass through a first charging current provided by the boot-strap capacitor when the first control signal is asserted; and a slew-rate control capacitor, where a first terminal of the slew-rate control capacitor is coupled to the first node.
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公开(公告)号：US20250088090A1
公开(公告)日：2025-03-13
申请号：US18829765
申请日：2024-09-10
Applicant: STMicroelectronics International N.V.
Inventor： Alessandro BERTOLINI , Germano NICOLLINI , Alessandro GASPARINI , Alberto BRUNERO , Alberto CATTANI
Abstract: A time-based DC-DC converter is controlled in response to a first oscillator signal based on a first control signal, a second oscillator signal based on a second control signal and a controlled current based on a feedback control signal. The first control signal and the second control signal are a function of the controlled current. The feedback control signal is generated as a function of the first and second oscillator signals by: generating at least two binary signals including a first binary signal based on a difference between the first oscillator signal and the reference signal and a second binary signal based on a difference between the second oscillator signal and the reference signal; and generating via a charge pump the feedback control signal based on the first binary signal and the second binary signal.
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公开(公告)号：US20250087605A1
公开(公告)日：2025-03-13
申请号：US18784674
申请日：2024-07-25
Applicant: STMicroelectronics International N.V.
Inventor： Antoine Le Ravallec , David Gaidioz , Christophe Arricastres
IPC: H01L23/66 , H01L23/00 , H01L23/522 , H01L23/528 , H01L25/065
Abstract: The present description concerns a device adapted to transmitting and receiving signals with a same antenna, comprising first, second, and third windings, the first and second windings being coupled so as to transmit the signals to be transmitted by the antenna, the first and third windings being coupled so as to transmit the signals received by the antenna, the device comprising first and second chips, the first chip comprising the antenna and the first winding, and the second chip comprising a winding from among the second and third windings, the first and second chips being bonded to each other by molecular bonding.
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