公开(公告)号：US09097582B2

公开(公告)日：2015-08-04

申请号：US13669119

申请日：2012-11-05

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Stuart McLeod

IPC: G01J1/44 ,  G01J1/42 ,  F21V23/04 ,  G01J3/51 ,  G01J1/04

CPC classification number: G01J1/42 ,  F21V23/0464 ,  G01J1/0407 ,  G01J1/0418 ,  G01J1/0488 ,  G01J1/4204 ,  G01J1/44 ,  G01J3/513

Abstract: A sensor for range finding and ambient light measurement wherein the sensor includes an array of pixels capable of sensing illumination in a plurality of wavelengths and generating a response thereto for each wavelength; the sensor including an ambient light sensing system which includes a module for adjusting the response from the ambient light sensor, such that the response for each wavelength is independent of the wavelength of the illumination.

Abstract translation: 一种用于测距和环境光测量的传感器，其中所述传感器包括能够感测多个波长的照明并为每个波长产生响应的像素阵列; 传感器包括环境光感测系统，其包括用于调节来自环境光传感器的响应的模块，使得每个波长的响应与照明的波长无关。

公开(公告)号：US09087756B2

公开(公告)日：2015-07-21

申请号：US13710198

申请日：2012-12-10

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Robert Golding

IPC: H04N5/76 ,  H04N9/64 ,  H04N5/335 ,  H01L27/146 ,  H04N5/355 ,  H04N5/378 ,  G01N21/64

CPC classification number: H01L27/14609 ,  G01N21/645 ,  H04N5/335 ,  H04N5/35572 ,  H04N5/378

Abstract: A pixel readout circuit including at least first, second and third memory locations. During an integration period of a pixel, the pixel readout circuit repeatedly samples the pixel output level during the integration period, stores the first sample in the first memory location, and stores each subsequent sample in memory locations other than the first memory location. Each sample is stored with a time corresponding to when that sample was taken, such that at any one time subsequent to the first three samples having been stored, at least the first sample and the two most recent samples are stored. Also disclosed is a corresponding method of reading out of a pixel output over an undefined integration period.

Abstract translation: 一种像素读出电路，至少包括第一，第二和第三存储单元。 在像素的积分期间，像素读出电路在积分期间反复取样像素输出电平，将第一样本存储在第一存储器位置，并将每个后续样本存储在第一存储单元以外的存储位置。 存储每个样品的时间对应于该采样时间，使得在存储了前三个样品之后的任何一个时间，至少存储了第一样品和两个最近的样品。 还公开了一种在未定义的积分周期内读出像素输出的相应方法。

公开(公告)号：US20130097401A1

公开(公告)日：2013-04-18

申请号：US13650503

申请日：2012-10-12

Applicant: STMicroelectronics (R&D) Ltd.

Inventor： Davide Sarta

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G06F12/06 ,  G06F12/0607

Abstract: A memory management device including a plurality of outputs, each output configured to interface to respective one of a plurality of memories; and a controller configured to cause each buffer allocated to the memories to be divided up substantially equally between each of the plurality of memories.

Abstract translation: 一种包括多个输出的存储器管理装置，每个输出被配置为与多个存储器中的相应的一个存储器接口; 以及控制器，其被配置为使得分配给所述存储器的每个缓冲器在所述多个存储器中的每一个之间基本上相等地被划分。