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    Method of manufacturing multilayer wiring substrate
    21.
    发明授权
    Method of manufacturing multilayer wiring substrate 失效
    制造多层布线基板的方法

    公开(公告)号：US08535546B2

    公开(公告)日：2013-09-17

    申请号：US13312534

    申请日：2011-12-06

    Applicant: Shinnosuke Maeda

    Inventor： Shinnosuke Maeda

    IPC: H01B13/00

    CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/205 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/054 ,  H01L2924/00

    Abstract: In order to provide a method of manufacturing a multilayer wiring substrate, a base member having a copper foil separably laminated thereon is prepared, and a solder resist layer is formed on the copper foil. Openings are formed in the solder resist layer, and a metal conductor portion is formed in each of the openings. By means of sputtering, a dissimilar metal layer is formed over the surface of the metal conductor portion and the entire surface of the solder resist layer. Copper electroplating is performed so as to form connection terminals and a conductor layer on the dissimilar metal layer. After a build-up step, the base material is removed, whereby the copper foil is exposed, and the exposed copper foil and the metal conductor portion are removed through etching, whereby the surfaces of the external connection terminals are exposed from the openings.

    Abstract translation: 为了提供一种制造多层布线基板的方法，制备了具有可分离层压在其上的铜箔的基底构件，并且在铜箔上形成阻焊层。 在阻焊层中形成开口，并且在每个开口中形成金属导体部。 通过溅射，在金属导体部分的表面和阻焊层的整个表面上形成不同的金属层。 进行铜电镀，以在异种金属层上形成连接端子和导体层。 在堆积步骤之后，除去基材，由此露出铜箔，通过蚀刻去除暴露的铜箔和金属导体部分，从而使外部连接端子的表面从开口露出。

    MULTILAYER WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    24.
    发明申请
    MULTILAYER WIRING SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
    多层布线基板及其制造方法

    公开(公告)号：US20120153463A1

    公开(公告)日：2012-06-21

    申请号：US13324535

    申请日：2011-12-13

    Applicant: Shinnosuke MAEDA

    Inventor： Shinnosuke MAEDA

    IPC: H01L23/498 ,  H05K1/00 ,  H05K3/10 ,  H05K1/11

    CPC classification number: H01L23/5226 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/0035 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2203/108 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: To provide a multilayer wiring substrate in which the connection reliability of via conductors is enhanced, via holes are formed in a resin interlayer insulation layer which isolates a lower conductor layer from an upper conductor layer, and via conductors are formed in the via holes for connecting the lower conductor layer and the upper conductor layer. The surface of the resin interlayer insulation layer is a rough surface, and the via holes open at the rough surface of the resin interlayer insulation layer. Stepped portions are formed in opening verge regions around the via holes such that the stepped portions are recessed from peripheral regions around the opening verge regions. The stepped portions are higher in surface roughness than the peripheral regions.

    Abstract translation: 为了提供通孔导体的连接可靠性提高的多层布线基板，在将下导体层与上导体层隔离的树脂层间绝缘层中形成通孔，并且通孔形成在用于连接的通孔中 下导体层和上导体层。 树脂层间绝缘层的表面是粗糙表面，并且通孔在树脂层间绝缘层的粗糙表面开口。 步进部分形成在通孔周围的打开边缘区域中，使得阶梯部分从围绕开口边缘区域的周边区域凹陷。 阶梯部分的表面粗糙度高于外围区域。

    Multilayered wiring board and method of manufacturing the same
    27.
    发明授权
    Multilayered wiring board and method of manufacturing the same 失效
    多层接线板及其制造方法

    公开(公告)号：US08389871B2

    公开(公告)日：2013-03-05

    申请号：US13034792

    申请日：2011-02-25

    Applicant: Shinnosuke Maeda ,  Satoshi Hirano

    Inventor： Shinnosuke Maeda ,  Satoshi Hirano

    IPC: H05K1/11

    CPC classification number: H05K3/4682 ,  H05K1/112 ,  H05K3/205 ,  H05K2201/094 ,  H05K2201/09472 ,  H05K2201/099 ,  Y10T29/49147

    Abstract: A multilayered wiring board having a stack structure multilayered by alternately stacking a plurality of conductor layers and a plurality of resin insulation layers, wherein a solder resist is provided on at least one of a first main surface side and a second main surface side of the stack structure, a plurality of openings are formed in an outermost resin insulation layer that contacts with the solder resist, a plurality of the first main surface side connecting terminals or a plurality of the second main surface side connecting terminals being made of a copper layer as a main component and positioned in a plurality of the openings, terminal outer surfaces being positioned inwardly from an outer surface of the outermost resin insulation layer, and the solder resist extends into the plurality of openings and makes contact with an outer circumference portion of each of the terminal outer surfaces.

    Abstract translation: 一种多层布线基板，其具有通过交替堆叠多个导体层和多个树脂绝缘层而叠层的叠层结构，其中在所述堆叠的第一主表面侧和第二主表面侧中的至少一个上设置阻焊剂 结构中，在与阻焊剂接触的最外层树脂绝缘层中形成多个开口，多个第一主表面侧连接端子或多个第二主表面侧连接端子由铜层制成， 主要部件并且定位在多个开口中，端子外表面从最外层树脂绝缘层的外表面向内定位，并且阻焊剂延伸到多个开口中并与每个的外周部分接触 端子外表面。

    METHOD OF MANUFACTURING MULTILAYER WIRING SUBSTRATE
    28.
    发明申请
    METHOD OF MANUFACTURING MULTILAYER WIRING SUBSTRATE 审中-公开
    制造多层布线基板的方法

    公开(公告)号：US20120097319A1

    公开(公告)日：2012-04-26

    申请号：US13280619

    申请日：2011-10-25

    Applicant: Shinnosuke Maeda

    Inventor： Shinnosuke Maeda

    IPC: B32B37/14 ,  B32B37/02

    CPC classification number: H05K3/426 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/0032 ,  H05K3/108 ,  H05K3/4602 ,  H05K2201/09563 ,  H05K2203/1572 ,  H01L2924/00

    Abstract: A method of manufacturing a multilayer wiring substrate of the present invention includes a preparation step of preparing a sheet-like insulation core having a thickness of 100 μm or less; a drilling step of forming through-holes which are open at a front surface and a back surface of the insulation core by subjecting the insulation core to laser drilling; a conductor forming step of forming, through electroless copper plating and subsequent copper electroplating, through-hole conductors which completely fill the corresponding through-holes of the insulation core and a respective conductor layer on each of the front surface and the back surface of the insulation core; and a lamination step of laminating a plurality of resin insulation layers and a plurality of conductor layers alternately in multilayer arrangement on each respective conductor layer on the front surface and the back surface of the insulation core.

    Abstract translation: 本发明的多层布线基板的制造方法包括：制备厚度为100μm以下的片状绝缘芯的制备工序; 钻孔步骤，通过对绝缘芯进行激光钻孔，形成在绝缘芯的前表面和后表面处开口的通孔; 导体形成步骤，通过化学镀铜和随后的铜电镀形成完全填充绝缘芯的相应通孔的通孔导体和绝缘体的前表面和后表面中的每一个上的相应导体层 核心; 以及层压步骤，在绝缘芯的前表面和后表面上的每个相应的导体层上层叠多个树脂绝缘层和多个导体层，多层布置。

    MULTILAYER WIRING SUBSTRATE
    29.
    发明申请
    MULTILAYER WIRING SUBSTRATE 有权
    多层布线基板

    公开(公告)号：US20110232951A1

    公开(公告)日：2011-09-29

    申请号：US13070094

    申请日：2011-03-23

    Applicant: Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

    Inventor： Shinnosuke MAEDA ,  Tatsuya ITO ,  Satoshi HIRANO

    IPC: H05K1/09

    CPC classification number: H05K3/244 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/4682 ,  H05K2201/099 ,  H05K2203/0361 ,  H01L2924/00

    Abstract: In a wiring laminate portion of a multilayer wiring substrate, a solder resist layer having a plurality of openings is disposed on a main surface side of the laminate structure, and connection terminals are embedded in an outermost resin insulation layer in contact with the solder resist layer. Each of the connection terminals comprises a copper layer and a metallic layer formed of at least one type of metal other than copper. A main-surface-side circumferential portion of the copper layer is covered by the solder resist layer. At least a portion of the metallic layer is located in a recess in a main-surface-side central portion of the copper layer. At least a portion of the metallic layer is exposed via a corresponding opening.

    Abstract translation: 在多层布线基板的布线层叠部分中，具有多个开口的阻焊层设置在层叠结构的主表面侧，并且连接端子嵌入在与阻焊层接触的最外层树脂绝缘层中 。 每个连接端子包括铜层和由铜以外的至少一种类型的金属形成的金属层。 铜层的主表面侧圆周部分被阻焊层覆盖。 金属层的至少一部分位于铜层的主表面侧中央部的凹部中。 金属层的至少一部分经由相应的开口露出。

    Multilayer wiring substrate
    30.
    发明授权
    Multilayer wiring substrate 有权
    多层布线基板

    公开(公告)号：US08847082B2

    公开(公告)日：2014-09-30

    申请号：US13109521

    申请日：2011-05-17

    Applicant: Shinnosuke Maeda ,  Satoshi Hirano

    Inventor： Shinnosuke Maeda ,  Satoshi Hirano

    IPC: H05K1/11 ,  H05K3/46 ,  H05K3/34 ,  H05K3/24

    CPC classification number: H05K1/113 ,  H05K3/244 ,  H05K3/3436 ,  H05K3/4682 ,  H05K2201/09472

    Abstract: To provide a multilayer wiring substrate which can prevent migration of copper between wiring traces to thereby realize a higher degree of integration, a solder resist layer 25 having a plurality of openings 35, 36 is disposed on a top surface 31 side, and IC-chip connection terminals 41 and capacitor connection terminals 42 are buried in an outermost resin insulation layer 23 in contact with the solder resist layer 25. Each of the IC-chip connection terminals 41 and the capacitor connection terminals 42 is composed of a copper layer 44 and a plating layer 46 covering the outer surface of the copper layer 44. A conductor layer 26 present at the interface between the solder resist layer 25 and the resin insulation layer 23 is composed of a copper layer 27 and a nickel plating layer 28 covering the outer surface of the copper layer 27.

    Abstract translation: 为了提供能够防止布线迹线之间的铜迁移从而实现更高的集成度的多层布线基板，具有多个开口部35,36的阻焊层25设置在顶面31侧，IC芯片 连接端子41和电容器连接端子42埋在与阻焊层25接触的最外层树脂绝缘层23中。每个IC芯片连接端子41和电容器连接端子42由铜层44和 镀覆层46覆盖铜层44的外表面。存在于阻焊层25和树脂绝缘层23之间的界面处的导体层26由铜层27和覆盖外表面的镀镍层28构成 的铜层27。

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