公开(公告)号：US20110097553A1

公开(公告)日：2011-04-28

申请号：US12631624

申请日：2009-12-04

Applicant: Jong Kuk Hong ,  Soon Jin Cho ,  Sun Uk Hwang

Inventor： Jong Kuk Hong ,  Soon Jin Cho ,  Sun Uk Hwang

IPC: H05K1/03 ,  B32B3/30 ,  H05K3/00

CPC classification number: H05K3/0032 ,  H05K1/036 ,  H05K1/0366 ,  H05K3/045 ,  H05K3/107 ,  H05K2201/0209 ,  H05K2201/029 ,  Y10T428/2462

Abstract: Disclosed is a trench substrate, which includes a first insulating layer having trenches formed therein, a second insulating layer disposed on a lower surface of the first insulating layer and having laser processability inferior to that of the first insulating layer, and a negative pattern formed in the trenches, and in which the second insulating layer having laser processability inferior to that of the first insulating layer functions as a stopper, so that the trenches having the same shape are formed in the first insulating layer, thus enabling the formation of a fine and uniform circuit pattern. A method of fabricating the trench substrate is also provided.

Abstract translation: 公开了一种沟槽衬底，其包括其中形成有沟槽的第一绝缘层，设置在第一绝缘层的下表面上并且具有劣于第一绝缘层的激光加工性的第二绝缘层，以及形成在 沟槽，其中具有劣于第一绝缘层的激光加工性的第二绝缘层用作止动件，使得具有相同形状的沟槽形成在第一绝缘层中，从而能够形成微细的和 均匀的电路图案。 还提供了制造沟槽衬底的方法。

公开(公告)号：US20090087950A1

公开(公告)日：2009-04-02

申请号：US12010544

申请日：2008-01-25

Applicant: Soon-Jin Cho ,  Jin-Won Choi ,  Seung-Hyun Cho ,  Chung-Woo Cho ,  Dong-Gyu Lee ,  Seok-Hwan Ahn

Inventor： Soon-Jin Cho ,  Jin-Won Choi ,  Seung-Hyun Cho ,  Chung-Woo Cho ,  Dong-Gyu Lee ,  Seok-Hwan Ahn

IPC: H01L21/58

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/00014

Abstract: A wafer packaging method is disclosed.An aspect of the invention is to provide a wafer packaging method comprising; attaching tape onto one side of a carrier, the carrier having a through-hole formed therein; attaching a wafer onto the tape exposed inside the through-hole such that at least one electrode of the wafer is exposed; and performing a packaging process on the carrier such that the wafer is packaged.

Abstract translation: 公开了一种晶片封装方法。 本发明的一个方面是提供一种晶片封装方法，包括： 将带附着到载体的一侧上，所述载体具有形成在其中的通孔; 将晶片附接到暴露在通孔内的带上，使得晶片的至少一个电极露出; 以及在所述载体上执行封装处理以使所述晶片被封装。

公开(公告)号：US20070018335A1

公开(公告)日：2007-01-25

申请号：US11483844

申请日：2006-07-11

Applicant: Seung-Hyun Cho ,  Soon-Jin Cho ,  Jae-Joon Lee ,  Se-Jong Oh

Inventor： Seung-Hyun Cho ,  Soon-Jin Cho ,  Jae-Joon Lee ,  Se-Jong Oh

IPC: H01L23/48

CPC classification number: H01L23/13 ,  H01L23/562 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2924/15162 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: A flip chip BGA board is disclosed, in which each of the corners of the board is removed to minimize warpage of the board due to heat applied during the manufacturing process. Embodiments of the invention allow the production of thin boards by preventing warpage of the board, and may provide a board high in reliability since the risk of the chip being separated from the board is reduced.

Abstract translation: 公开了一种倒装芯片BGA板，其中去除板的每个拐角以最小化由于在制造过程中施加的热而引起的板的翘曲。 本发明的实施例允许通过防止板的翘曲来生产薄板，并且可以提供高可靠性的板，因为芯片与板分离的风险降低。

公开(公告)号：US06400021B1

公开(公告)日：2002-06-04

申请号：US09604040

申请日：2000-06-27

Applicant: Soon Jin Cho

Inventor： Soon Jin Cho

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/3107 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/013

Abstract: Disclosed is a wafer level package and a method for fabricating the wafer level package, in which the contact area between the ball land and the solder ball is enlarged, so that the adhesion force between them is highly strengthened. The wafer level package has a semiconductor chip having a lower dielectric layer formed at a bond pad forming surface thereof. The lower dielectric layer includes vias and grooves, and the bond pads are exposed through the vias. A metal pattern interconnecting the bond pads and the grooves with each other is deposited on the lower dielectric layer. An upper dielectric layer is applied on the lower dielectric layer. The upper dielectric layer has a ball land through which the metal pattern deposited on a surface of the grooves is exposed. A solder ball is mounted on the ball land.

Abstract translation: 公开了一种用于制造晶片级封装的晶片级封装和方法，其中，焊盘和焊球之间的接触面积增大，使得它们之间的粘附力得到高度的增强。 晶片级封装具有在其接合焊盘形成表面形成有下介电层的半导体芯片。 下介电层包括通孔和沟槽，并且接合焊盘通过通孔露出。 将接合焊盘和沟槽彼此互连的金属图案沉积在下介电层上。 在下电介质层上施加上电介质层。 上电介质层具有暴露出凹槽表面上沉积的金属图案的球台。 焊球安装在球面上。

公开(公告)号：US06222259B1

公开(公告)日：2001-04-24

申请号：US09393869

申请日：1999-09-10

Applicant: Sang Wook Park ,  Soon Jin Cho

Inventor： Sang Wook Park ,  Soon Jin Cho

IPC: H01L2348

CPC classification number: H01L24/48 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3107 ,  H01L24/45 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/05599 ,  H01L2224/451 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/48465 ,  H01L2224/4899 ,  H01L2224/85399 ,  H01L2225/06506 ,  H01L2225/0652 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2924/00012

Abstract: Disclosed is a stack package and a method of manufacturing the same. The stack package of the present invention comprises a ceramic capsule. A pair of protruding portions are formed at both upper sides of the ceramic capsule. A first semiconductor chip is attached on the upper face of the ceramic capsule and a second semiconductor chip is attached on a lower face of the ceramic capsule. The first and second semiconductor chips are disposed such that their bonding pads are disposed upwardly, more particularly the second semiconductor chip has a size that its bonding pad may be exposed from both sides of the ceramic capsule. It is preferable to attach a heatsink at the lower face of the second semiconductor chip. The first and second semiconductor chips are electrically connected with a metal wire. A midway portion of the metal wire is laid on the protruding portion of the ceramic capsule. The entire resultant is encapsulated with a molding compound while exposing the portion of metal wire laid on the protruding portion and the heatsink. A conductive bump is formed on the exposed portion of the metal wire, and a solder ball is mounted on the conductive bump.

Abstract translation: 公开了一种堆叠包装及其制造方法。 本发明的堆叠包括陶瓷胶囊。 在陶瓷胶囊的两个上侧形成有一对突出部。 第一半导体芯片附着在陶瓷胶囊的上表面上，第二半导体芯片附着在陶瓷胶囊的下表面上。 第一半导体芯片和第二半导体芯片被布置成使得它们的焊盘向上设置，更具体地，第二半导体芯片的尺寸使得其焊盘可以从陶瓷胶囊的两侧露出。 优选在第二半导体芯片的下表面附接散热器。 第一和第二半导体芯片与金属线电连接。 金属线的中间部分铺设在陶瓷胶囊的突出部分上。 整个产物用模塑料封装，同时暴露放置在突出部分和散热器上的金属线的部分。 在金属线的暴露部分上形成导电凸块，并且在导电凸块上安装焊球。

公开(公告)号：US08535547B2

公开(公告)日：2013-09-17

申请号：US12010195

申请日：2008-01-22

Applicant: Chung-Woo Cho ,  Soon-Jin Cho ,  Byung-Bae Seo ,  Ki-Young Yoo ,  Seok-Hwan Ahn

Inventor： Chung-Woo Cho ,  Soon-Jin Cho ,  Byung-Bae Seo ,  Ki-Young Yoo ,  Seok-Hwan Ahn

IPC: H01B13/00

CPC classification number: H05K3/0008 ,  H05K1/0269 ,  H05K3/0035 ,  H05K3/4644 ,  H05K3/4679 ,  H05K2201/0108 ,  H05K2201/09918

Abstract: A printed circuit board manufacturing system and a manufacturing method thereof are disclosed. A method of manufacturing printed circuit board, comprising: providing a substrate that comprises a pad and an insulation layer covering the pad; acquiring an image of the substrate; acquiring location information of the pad by analyzing the image of the substrate; forming a via hole by removing a part of the insulation layer that corresponds the location information of the pad; and forming a via by filling the via hole with a conductive material, provides improved process conformity, even if the substrate has partial or nonlinear deformation, by considering the location information of the pad in the via hole forming. The improved conformity may allow more flexibility to substrate design and more integrity for circuitries on printed circuit board.

公开(公告)号：US08074352B2

公开(公告)日：2011-12-13

申请号：US12213365

申请日：2008-06-18

Applicant: Dong-Jin Park ,  Seung-Hyun Jung ,  Seung-Chul Kim ,  Soon-Jin Cho

Inventor： Dong-Jin Park ,  Seung-Hyun Jung ,  Seung-Chul Kim ,  Soon-Jin Cho

IPC: H05K3/04 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K3/107 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/045 ,  H05K3/421 ,  H05K3/427 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2203/0577 ,  H05K2203/0723 ,  H05K2203/1152 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method of manufacturing a printed circuit board is disclosed. The method may include: sequentially stacking an acid-resistant first cover layer and an alkali-resistant second cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the second cover layer, the first cover layer, and the copper clad laminate; stacking a seed layer over the intaglio groove and the second cover layer; removing a portion of the seed layer stacked over the second cover layer, by stripping the second cover layer; forming a plating layer, by plating an inside of the intaglio groove; stripping the first cover layer; and removing the copper foil exposed by the stripping of the first cover layer.

Abstract translation: 公开了一种制造印刷电路板的方法。 该方法可以包括：在铜箔上顺序层叠耐酸性第一覆盖层和耐碱性第二覆盖层，对于包含层叠在绝缘层一侧的铜箔的覆铜层压板， 通过去除第二覆盖层，第一覆盖层和覆铜层压板的部分来形成凹版凹槽; 将种子层堆叠在凹版凹槽和第二覆盖层上; 通过剥离所述第二覆盖层去除层叠在所述第二覆盖层上的所述种子层的一部分; 通过电镀凹版凹槽的内部形成镀层; 剥离第一覆盖层; 以及去除通过剥离第一覆盖层而暴露的铜箔。

公开(公告)号：US20100271792A1

公开(公告)日：2010-10-28

申请号：US12612158

申请日：2009-11-04

Applicant: Jin-Won Choi ,  Soon-Jin Cho ,  Hueng-Jae Oh ,  Seung-Wan Kim ,  Seon-Jae Mun

Inventor： Jin-Won Choi ,  Soon-Jin Cho ,  Hueng-Jae Oh ,  Seung-Wan Kim ,  Seon-Jae Mun

IPC: H05K7/02 ,  B23K31/02

CPC classification number: B23K1/0016 ,  B23K2101/42 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H05K3/243 ,  H05K3/3452 ,  H05K2201/0367 ,  H05K2201/0989 ,  H05K2203/054 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: An electronic component package and a method of manufacturing the same are disclosed. The method can include: providing a board, on which a multiple number of pads are formed; forming a solder resist layer, in which an opening superimposing over all of the pads is formed, on the board; forming metal posts over the pads, respectively; mounting an electronic component on the board by bonding the electrodes to the metal posts; and forming an underfill resin layer in the opening such that the underfill resin layer is interposed between the electronic component and the board. The solder resist layer may function as a dam that prevents the underfill resin layer from leaking in lateral directions during the subsequent underfill process so that the additional processes, such as dispensing, etc., that were required for forming a separate dam can be omitted, and the process time and costs can be reduced.

Abstract translation: 公开了一种电子部件封装及其制造方法。 该方法可以包括：提供一个板，其上形成多个焊盘; 形成阻焊层，其中在所述板上形成叠加在所有焊盘上的开口; 分别在焊盘上形成金属柱; 通过将电极粘合到金属柱上来将电子部件安装在电路板上; 并且在开口中形成底部填充树脂层，使得底部填充树脂层插入在电子部件和板之间。 阻焊层可以用作防止底部填充树脂层在随后的底部填充过程中在侧向泄漏的坝，从而可以省略形成单独的坝所需的附加过程，例如分配等， 并且可以减少处理时间和成本。

公开(公告)号：US20090183909A1

公开(公告)日：2009-07-23

申请号：US12382293

申请日：2009-03-12

Applicant: Soon-Jin CHO

Inventor： Soon-Jin CHO

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K3/06 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: A coreless substrate having a plurality of function pads, etched from a metal sheet and having a protruded shape; an insulating layer, the insulating layer being formed on one side of the function pads, a circuit corresponding to a pattern being formed on the insulating layer, a via hole being formed on the insulating layer to electrically connect the function pads and the circuit; and a solder resist, being formed on the insulating layer to protect the surface of the insulating layer. The coreless substrate has a signal delivery characteristic that is improved by eliminating the inner via hole.

Abstract translation: 一种无芯基板，具有从金属板蚀刻并具有突出形状的多个功能垫; 绝缘层，所述绝缘层形成在所述功能焊盘的一侧上，对应于在所述绝缘层上形成的图案的电路，形成在所述绝缘层上以电连接所述功能焊盘和所述电路的通孔; 和阻焊层，形成在绝缘层上以保护绝缘层的表面。 无芯基板具有通过消除内通孔而改善的信号传递特性。

公开(公告)号：US20070084630A1

公开(公告)日：2007-04-19

申请号：US11542175

申请日：2006-10-04

Applicant: Soon-Jin Cho

Inventor： Soon-Jin Cho

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K3/06 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: The present invention discloses a method for manufacturing a coreless substrate. The method comprises the steps of (a) forming an insulating layer on one side of a metal sheet; (b) forming a via hole on the insulating layer for electrical connection between the metal sheet and the other side; and (c) forming a plurality of protruded function pads by etching the metal sheet. The coreless substrate and manufacturing method thereof in accordance with the present invention have the signal delivery characteristic that is improved by eliminating the inner via hole.

Abstract translation: 本发明公开了一种无芯基板的制造方法。 该方法包括以下步骤：（a）在金属片的一侧上形成绝缘层; （b）在绝缘层上形成用于金属片和另一侧之间的电连接的通孔; 和（c）通过蚀刻金属板形成多个突出的功能垫。 根据本发明的无芯基板及其制造方法具有通过消除内通孔而提高的信号传递特性。