公开(公告)号：US20210202412A1

公开(公告)日：2021-07-01

申请号：US16730390

申请日：2019-12-30

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Lin SHIH ,  Chih-Cheng LEE

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/528

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a circuit structure. The circuit structure includes a dielectric layer and a bonding pad. The dielectric layer has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface, where the dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall. The bonding pad is disposed in the recess, where a first pad surface of the bonding pad is adjacent to the first dielectric surface, a second pad surface of the bonding pad is adjacent to the second dielectric surface, and an edge of the bonding pad is spaced from the sidewall of the recess by a first distance.

公开(公告)号：US20210125909A1

公开(公告)日：2021-04-29

申请号：US17140926

申请日：2021-01-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Chun Chen CHEN ,  Chen Yuang CHEN

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H05K1/18 ,  H05K3/34 ,  H01L21/48

Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.

公开(公告)号：US20200211948A1

公开(公告)日：2020-07-02

申请号：US16814729

申请日：2020-03-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48

Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

公开(公告)号：US20200161743A1

公开(公告)日：2020-05-21

申请号：US16197352

申请日：2018-11-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01Q1/22 ,  H01Q9/04 ,  H01Q21/06 ,  H01L23/66 ,  H01Q23/00 ,  H01Q21/00 ,  H01L23/00

Abstract: An antenna package includes a patterned antenna structure and an encapsulant. The patterned antenna structure includes a first surface, a second surface opposite the first surface and a third surface extended between the first surface and the second surface. The encapsulant is disposed on the first surface of the patterned antenna structure. The third surface of the patterned antenna structure includes a first portion covered by the encapsulant and a second portion exposed from the encapsulant.

公开(公告)号：US20200027810A1

公开(公告)日：2020-01-23

申请号：US16038037

申请日：2018-07-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/367 ,  H01L21/768 ,  H01L23/373 ,  H01L23/00

Abstract: The present disclosure provides a semiconductor substrate, including a first patterned conductive layer, a dielectric structure on the first patterned conductive layer, wherein the dielectric structure having a side surface, a second patterned conductive layer on the dielectric structure and extending on the side surface, and a third patterned conductive layer on the second patterned conductive layer and extending on the side surface. The present disclosure provides a semiconductor package including the semiconductor substrate. A method for manufacturing the semiconductor substrate and the semiconductor package is also provided.

公开(公告)号：US20190252305A1

公开(公告)日：2019-08-15

申请号：US15893180

申请日：2018-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Shu PENG ,  Cheng-Lin HO ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49816 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2224/16235

Abstract: A substrate includes a first dielectric layer having a first surface and a second surface opposite to the first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer and comprising an interconnection structure, and an interconnection element. The interconnection element extends from the first surface of the first dielectric layer to the second surface of the first dielectric layer and is surrounded by the interconnection structure.

公开(公告)号：US20180130759A1

公开(公告)日：2018-05-10

申请号：US15348899

申请日：2016-11-10

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Lin HO ,  Chih-Cheng LEE ,  Li-Chuan TSAI

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49811 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81385 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/35121 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.

公开(公告)号：US20180005846A1

公开(公告)日：2018-01-04

申请号：US15630847

申请日：2017-06-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li Chuan TSAI ,  Chih-Cheng LEE ,  Cheng-Lin HO

IPC: H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L21/4857 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/498 ,  H01L24/16

Abstract: A substrate includes a dielectric layer having a first surface and a second surface opposite to the first surface, a first circuit layer and at least one second conductive element. The first circuit layer is disposed adjacent to the first surface of the dielectric layer, and includes at least one trace and at least one first conductive element connected to the trace. The first conductive element does not extend through the dielectric layer. The second conductive element extends through the dielectric layer. An area of an upper surface of the second conductive element is substantially equal to an area of an upper surface of the first conductive element.

公开(公告)号：US20170077023A1

公开(公告)日：2017-03-16

申请号：US15364143

申请日：2016-11-29

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H01L23/498 ,  H05K1/11 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: A semiconductor substrate includes: 1) a first dielectric structure having a first surface and a second surface opposite the first surface; 2) a second dielectric structure having a third surface and a fourth surface opposite the third surface, wherein the fourth surface faces the first surface, the second dielectric structure defining a through hole extending from the third surface to the fourth surface, wherein a cavity is defined by the through hole and the first dielectric structure; 3) a first patterned conductive layer, disposed on the first surface of the first dielectric structure; and 4) a second patterned conductive layer, disposed on the second surface of the first dielectric structure and including at least one conductive trace. The first dielectric structure defines at least one opening to expose a portion of the second patterned conductive layer.

Abstract translation: 半导体衬底包括：1）具有第一表面和与第一表面相对的第二表面的第一电介质结构; 2）具有与第三表面相对的第三表面和第四表面的第二介电结构，其中第四表面面向第一表面，第二介电结构限定从第三表面延伸到第四表面的通孔，其中腔是 由通孔和第一电介质结构限定; 3）设置在第一介电结构的第一表面上的第一图案化导电层; 以及4）第二图案化导电层，设置在所述第一介电结构的第二表面上并且包括至少一个导电迹线。 第一介电结构限定至少一个开口以暴露第二图案化导电层的一部分。

公开(公告)号：US20160240469A1

公开(公告)日：2016-08-18

申请号：US15138107

申请日：2016-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Cheng LEE ,  Yuan Chang Su ,  Cheng-Lin Ho ,  Chung-Ming Wu ,  You-Lung Yen

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/11334 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16113 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor package structure, and methods for making the same. A method includes providing a substrate and a carrier layer. The substrate includes a first patterned metal layer, a second patterned metal layer spaced from the first patterned metal layer, and a dielectric layer disposed between the first patterned metal layer and the second patterned metal layer. The dielectric layer covers the second patterned metal layer. The dielectric layer defines first openings exposing the second patterned metal layer, and further defines a via opening extending from the first patterned metal layer to the second patterned metal layer. A conductive material is disposed in the via and electrically connects the first patterned metal layer to the second patterned metal layer. The carrier layer defines second openings exposing the second patterned metal layer.