公开(公告)号：US11637043B2

公开(公告)日：2023-04-25

申请号：US17087976

申请日：2020-11-03

Applicant: Applied Materials, Inc.

Inventor： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC: H01L21/66 ,  G06F30/398 ,  G03F7/20

Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

公开(公告)号：US20230008922A1

公开(公告)日：2023-01-12

申请号：US17371549

申请日：2021-07-09

Applicant: Applied Materials, Inc.

Inventor： Saketh Pemmasani ,  Akshay Dhanakshirur ,  Mayur Govind Kulkarni ,  Madhu Santosh Kumar Mutyala ,  Hang Yu ,  Deenesh Padhi

IPC: H01L21/683 ,  H01J37/32 ,  C23C16/458

Abstract: Exemplary substrate support assemblies may include a chuck body defining a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. The substrate support surface may define an annular groove and/or ridge. A subset of the plurality of protrusions may be disposed within the annular groove and/or ridge. The substrate support assemblies may include a support stem coupled with the chuck body.

公开(公告)号：US20220415651A1

公开(公告)日：2022-12-29

申请号：US17361925

申请日：2021-06-29

Applicant: Applied Materials, Inc.

Inventor： Qixin Shen ,  Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi ,  Gill Yong Lee ,  Sung-Kwan Kang ,  Abdul Wahab Mohammed ,  Hailing Liu

IPC: H01L21/02 ,  H01L21/033 ,  H01L27/108

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on the ruthenium comprises pre-treating the ruthenium layer with a plasma to form an interface layer on the ruthenium layer; and forming a silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). Pre-treating the ruthenium layer, in some embodiments, results in the interface layer having a reduced roughness and the memory device having a reduced resistivity compared to a memory device that does not include the interface layer.

公开(公告)号：US11515145B2

公开(公告)日：2022-11-29

申请号：US17018173

申请日：2020-09-11

Applicant: Applied Materials, Inc.

Inventor： Chuanxi Yang ,  Hang Yu ,  Deenesh Padhi

IPC: H01L21/02 ,  C23C16/38 ,  C23C8/36 ,  C23C8/24 ,  H01L21/033

Abstract: Methods for forming a SiBN film comprising depositing a film on a feature on a substrate. The method comprises in a first cycle, depositing a SiB layer on a substrate in a chamber using a chemical vapor deposition process, the substrate having at least one feature thereon, the at least one feature comprising an upper surface, a bottom surface and sidewalls, the SiB layer formed on the upper surface, the bottom surface and the sidewalls. In a second cycle, the SiB layer is treated with a plasma comprising a nitrogen-containing gas to form a conformal SiBN film.

公开(公告)号：US11430654B2

公开(公告)日：2022-08-30

申请号：US16698500

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi

IPC: H01L21/31 ,  H01L21/02 ,  H01J37/32 ,  C23C16/458 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor into the processing region of the semiconductor processing chamber at a first flow rate. The methods may include ramping the first flow rate of the silicon-containing precursor over a period of time to a second flow rate greater than the first flow rate. The methods may include depositing a silicon-containing material on the semiconductor substrate.

公开(公告)号：US20220138396A1

公开(公告)日：2022-05-05

申请号：US17087976

申请日：2020-11-03

Applicant: Applied Materials, Inc.

Inventor： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC: G06F30/398 ,  H01L21/66

Abstract: Methods, systems, and non-transitory computer readable medium are described for generating assessment maps for corrective action. A method includes receiving a first vector map including a first set of vectors each indicating a distortion of a particular location of a plurality of locations on a substrate. The method further includes generating a second vector map including a second set of vectors by rotating a position of each vector in the first set of vectors. The method further includes generating a third vector map including a third set of vectors based on vectors in the second set of vectors and corresponding vectors in the first set of vectors. The method further includes generating a fourth vector map by subtracting each vector of the third set of vectors from a corresponding vector in the first set of vectors. The fourth vector map indicates a planar component of the first vector map.

公开(公告)号：US20220123114A1

公开(公告)日：2022-04-21

申请号：US17073060

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Akhil Singhal ,  Allison Yau ,  Sang-Jin Kim ,  Zeqiong Zhao ,  Zhijun Jiang ,  Deenesh Padhi ,  Ganesh Balasubramanian

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423

Abstract: Exemplary semiconductor structures and processing methods may include forming a first portion of a first semiconductor layer characterized by a first etch rate for an etch treatment, forming a second portion of the first semiconductor layer characterized by a second etch rate that is less than the first etch rate for the etch treatment, and forming a third portion of the first semiconductor layer characterized by a third etch rate that is greater than the second etch rate. The processing methods may further include etching an opening through the first semiconductor layer, where the opening has a height and a width, and where the opening is characterized by a variation in the width between a midpoint of the height of the opening and an endpoint of the opening that is less than or about 5 Å

公开(公告)号：US20220122811A1

公开(公告)日：2022-04-21

申请号：US17072673

申请日：2020-10-16

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi ,  Mayur Govind Kulkarni ,  Arun Thottappayil

IPC: H01J37/32 ,  H01L21/02 ,  C23C16/40 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.

公开(公告)号：US11157661B2

公开(公告)日：2021-10-26

申请号：US16716274

申请日：2019-12-16

Applicant: Applied Materials, Inc.

Inventor： Vinayak Veer Vats ,  Sidharth Bhatia ,  Garrett Ho-Yee Sin ,  Pramod Nambiar ,  Hang Yu ,  Sanjay Kamath ,  Deenesh Padhi ,  Heng-Cheng Pai

IPC: G06F30/12 ,  G06F16/904 ,  G06F16/903 ,  G06F119/18

Abstract: A process development visualization tool generates a first visualization of a parameter associated with a manufacturing process, and provides a GUI control element associated with a process variable of the manufacturing process, wherein the GUI control element has a first setting associated with a first value for the process variable. The process development tool receives a user input to adjust the GUI control element from the first setting to a second setting, determines a second value for the process variable based on the second setting, and determines a second set of values for the parameter that are associated with the second value for the process variable. The process development tool then generates a second visualization of the parameter, wherein the second visualization represents the second set of values for the parameter that are associated with the second value for the process variable.

公开(公告)号：US20210242016A1

公开(公告)日：2021-08-05

申请号：US16782933

申请日：2020-02-05

Applicant: Applied Materials, Inc.

Inventor： Madhu Santosh Kumar Mutyala ,  Sanjay Kamath ,  Deenesh Padhi

IPC: H01L21/02 ,  H01J37/32 ,  C23C16/40 ,  C23C16/50

Abstract: Exemplary deposition methods may include forming a plasma of a silicon-containing precursor and at least one additional precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include depositing material on the semiconductor substrate to a target thickness. The methods may include halting delivery of the silicon-containing precursor while maintaining the plasma with the one or more precursors. The methods may include purging the processing region of the semiconductor processing chamber.