公开(公告)号：US12110590B2

公开(公告)日：2024-10-08

申请号：US18381534

申请日：2023-10-18

Applicant: Applied Materials, Inc.

Inventor： Shailendra Srivastava ,  Sai Susmita Addepalli ,  Nikhil Sudhindrarao Jorapur ,  Daemian Raj Benjamin Raj ,  Amit Kumar Bansal ,  Juan Carlos Rocha-Alvarez ,  Gregory Eugene Chichkanoff ,  Xinhai Han ,  Masaki Ogata ,  Kristopher Enslow ,  Wenjiao Wang

IPC: C23C16/455 ,  C23C16/458 ,  C23C16/50 ,  H01J37/32

CPC classification number: C23C16/45565 ,  C23C16/45536 ,  C23C16/4583 ,  C23C16/50 ,  H01J37/3244 ,  H01J37/32458 ,  H01J2237/3321

Abstract: A faceplate for a substrate process chamber comprises a first and second surface. The second surface is shaped such that the second surface includes a peak and a distance between the first and second surface varies across the width of the faceplate. The second surface of the faceplate is exposed to a processing volume of the process chamber. Further, the faceplate may be part of a lid assembly for the process chamber. The lid assembly may include a blocker plate facing the first surface of the faceplate. A distance between the blocker plate and the first surface is constant.

公开(公告)号：US20230093330A1

公开(公告)日：2023-03-23

申请号：US17994936

申请日：2022-11-28

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L29/51

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with increased cell density. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells. Some embodiments form 3D NAND devices with smaller CD memory holes. Some embodiments form 3D NAND devices with silicon layer between alternating oxide and nitride materials.

公开(公告)号：US20220307131A1

公开(公告)日：2022-09-29

申请号：US17213908

申请日：2021-03-26

Applicant: Applied Materials, Inc.

Inventor： Anantha K. Subramani ,  Seyyed Abdolreza Fazeli ,  Yang Guo ,  Ramcharan Sundar ,  Arun Kumar Kotrappa ,  Steven Mosbrucker ,  Steven D. Marcus ,  Xinhai Han ,  Kesong Hu ,  Tianyang Li ,  Philip A. Kraus

IPC: C23C16/455 ,  C23C16/458 ,  H01J37/32 ,  C23C14/56

Abstract: Exemplary substrate processing systems may include a chamber body defining a transfer region. The systems may include a first lid plate seated on the chamber body. The first lid plate may define a plurality of apertures through the first lid plate. The systems may include a plurality of lid stacks equal to a number of the plurality of apertures. The systems may define a plurality of isolators. An isolator may be positioned between each lid stack and a corresponding aperture of the plurality of apertures. The systems may include a plurality of annular spacers. An annular spacer of the plurality of annular spacers may be positioned between each isolator and a corresponding lid stack of the plurality of lids stacks. The systems may include a plurality of manifolds. A manifold may be seated within an interior of each annular spacer of the plurality of annular spacers.

公开(公告)号：US20220068630A1

公开(公告)日：2022-03-03

申请号：US17009002

申请日：2020-09-01

Applicant: Applied Materials, Inc.

Inventor： Chuanxi Yang ,  Hang Yu ,  Yu Yang ,  Chuan Ying Wang ,  Allison Yau ,  Xinhai Han ,  Sanjay G. Kamath ,  Deenesh Padhi

IPC: H01L21/02 ,  C23C16/34

Abstract: Exemplary methods of semiconductor processing may include flowing a silicon-containing precursor, a nitrogen-containing precursor, and diatomic hydrogen into a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber. The methods may also include forming a plasma of the silicon-containing precursor, the nitrogen-containing precursor, and the diatomic hydrogen. The plasma may be formed at a frequency above 15 MHz. The methods may also include depositing a silicon nitride material on the substrate.

公开(公告)号：US11164882B2

公开(公告)日：2021-11-02

申请号：US16783425

申请日：2020-02-06

Applicant: Applied Materials, Inc.

Inventor： Thomas Kwon ,  Xinhai Han

IPC: H01L29/423 ,  H01L27/11524 ,  H01L21/28 ,  H01L27/11556

Abstract: Methods of forming 3D NAND devices are discussed. Some embodiments form 3D NAND devices with a control gate and a floating gate disposed between a first insulating layer and a second insulating layer. A conformal blocking liner surrounds the floating gate and electrically isolates the control gate from the floating gate. Some embodiments form 3D NAND devices with decreased vertical and/or later pitch between cells.

公开(公告)号：US20210040607A1

公开(公告)日：2021-02-11

申请号：US16986632

申请日：2020-08-06

Applicant: Applied Materials, Inc.

Inventor： Xinhai Han ,  Hang Yu ,  Kesong Hu ,  Kristopher Enslow ,  Masaki Ogata ,  Wenjiao Wang ,  Chuan Ying Wang ,  Chuanxi Yang ,  Joshua Maher ,  Phaik Lynn Leong ,  Qi En Teong ,  Alok Jain ,  Nagarajan Rajagopalan ,  Deenesh Padhi

IPC: C23C16/34 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/1157 ,  H01L27/11578 ,  C23C16/40

Abstract: Exemplary methods of forming semiconductor structures may include forming a silicon oxide layer from a silicon-containing precursor and an oxygen-containing precursor. The methods may include forming a silicon nitride layer from a silicon-containing precursor, a nitrogen-containing precursor, and an oxygen-containing precursor. The silicon nitride layer may be characterized by an oxygen concentration greater than or about 5 at. %. The methods may also include repeating the forming a silicon oxide layer and the forming a silicon nitride layer to produce a stack of alternating layers of silicon oxide and silicon nitride.

公开(公告)号：US09490116B2

公开(公告)日：2016-11-08

申请号：US14879043

申请日：2015-10-08

Applicant: Applied Materials, Inc.

Inventor： Michael Tsiang ,  Praket P. Jha ,  Xinhai Han ,  Nagarajan Rajagopalan ,  Bok Hoen Kim ,  Tsutomu Kiyohara ,  Subbalakshmi Sreekala

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L21/0217 ,  H01L21/02274 ,  H01L27/11582

Abstract: Embodiments of the disclosure provide methods and system for manufacturing film layers with minimum lithographic overlay errors on a semiconductor substrate. In one embodiment, a method for forming a film layer on a substrate includes supplying a deposition gas mixture including a silicon containing gas and a reacting gas onto a substrate disposed on a substrate support in a processing chamber, forming a plasma in the presence of the depositing gas mixture in the processing chamber, applying current to a plasma profile modulator disposed in the processing chamber while supplying the depositing gas mixture into the processing chamber, and rotating the substrate while depositing a film layer on the substrate.

Abstract translation: 本公开的实施例提供了在半导体衬底上制造具有最小光刻重叠误差的膜层的方法和系统。 在一个实施例中，用于在衬底上形成膜层的方法包括将包含含硅气体和反应气体的沉积气体混合物供给到设置在处理室中的衬底支撑体上的衬底上，在存在 在处理室中沉积气体混合物，将电流施加到设置在处理室中的等离子体轮廓调制器，同时将沉积气体混合物供应到处理室中，并且在衬底上沉积膜层的同时旋转衬底。

公开(公告)号：US11948846B2

公开(公告)日：2024-04-02

申请号：US18130500

申请日：2023-04-04

Applicant: Applied Materials, Inc.

Inventor： Wenjiao Wang ,  Joshua Maher ,  Xinhai Han ,  Deenesh Padhi ,  Tza-Jing Gung

IPC: H01L21/66 ,  G03F7/00 ,  G06F30/398

CPC classification number: H01L22/12 ,  G06F30/398 ,  G03F7/705

Abstract: Methods and systems are described for generating assessment maps. A method includes receiving a first vector map comprising a first set of vectors each indicating a distortion of a particular location on a substrate and generating a second vector map indicating a change in direction of a magnitude of the distortion of the particular location on the substrate. The method further includes generating a third vector map comprising vectors reflecting reduced noise in distortions across the plurality of locations on the substrate and generating a fourth vector map projecting a direction component of each vector component in the third set of vectors to a radial direction. The method further includes generating a fifth vector map by grouping the vectors of the fourth set of vectors and determining a magnitude associated with each group of vectors.

公开(公告)号：US11898249B2

公开(公告)日：2024-02-13

申请号：US18108989

申请日：2023-02-13

Applicant: Applied Materials, Inc.

Inventor： Nagarajan Rajagopalan ,  Xinhai Han ,  Michael Wenyoung Tsiang ,  Masaki Ogata ,  Zhijun Jiang ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Jianhua Zhou ,  Ramprakash Sankarakrishnan ,  Amit Kumar Bansal ,  Jeongmin Lee ,  Todd Egan ,  Edward W. Budiarto ,  Dmitriy Panasyuk ,  Terrance Y. Lee ,  Jian J. Chen ,  Mohamad A. Ayoub ,  Heung Lak Park ,  Patrick Reilly ,  Shahid Shaikh ,  Bok Hoen Kim ,  Sergey Starik ,  Ganesh Balasubramanian

IPC: C23C16/52 ,  G01B11/06 ,  H01L21/687 ,  H01L21/67 ,  C23C16/509 ,  G01N21/55 ,  G01N21/65 ,  H01L21/00 ,  C23C16/458 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/455

CPC classification number: C23C16/52 ,  C23C16/458 ,  C23C16/4557 ,  C23C16/45565 ,  C23C16/46 ,  C23C16/50 ,  C23C16/505 ,  C23C16/509 ,  C23C16/5096 ,  G01B11/0625 ,  G01B11/0683 ,  G01N21/55 ,  G01N21/658 ,  H01L21/00 ,  H01L21/67248 ,  H01L21/67253 ,  H01L21/687 ,  G01N2201/1222

Abstract: A method of processing a substrate according to a PECVD process is described. Temperature profile of the substrate is adjusted to change deposition rate profile across the substrate. Plasma density profile is adjusted to change deposition rate profile across the substrate. Chamber surfaces exposed to the plasma are heated to improve plasma density uniformity and reduce formation of low quality deposits on chamber surfaces. In situ metrology may be used to monitor progress of a deposition process and trigger control actions involving substrate temperature profile, plasma density profile, pressure, temperature, and flow of reactants.

公开(公告)号：US20240045399A1

公开(公告)日：2024-02-08

申请号：US18038441

申请日：2022-05-17

Applicant: Applied Materials, Inc.

Inventor： Qinglin Chai ,  Yue Ma ,  Liming Zhang ,  Xinhai Han ,  Chuan Ying Wang

IPC: G05B19/4099

CPC classification number: G05B19/4099 ,  G05B2219/45031

Abstract: A method includes receiving time trace sensor data associated with a substrate processing procedure. The substrate processing procedure includes two or more sets of processing conditions. At least a first set of processing conditions and a second set of processing conditions each include one or more operations performed repeatedly. The method further includes separating a first and second portion of the time trace sensor data corresponding to the first and second sets of processing conditions into a first and second plurality of cycle data. The method further includes processing the first plurality of cycle data and the second plurality of cycle data to generate summary data. The method further includes providing an alert to a user. The alert is based on the summary data.